The Class E Power Amplier

A switching amplier has improved eciency compared to a linear amplier by using the power transistor as a switch which is either fully on or fully o. When the switch is fully on, thenV_ds= 0, and when the switch is fully oI_ds= 0. Both of the states result in P = IV = 0, theoretically resulting in zero losses for 100% eciency. However, in reality, large currents will ow with considerable voltage drop during the transistor's transition from full on to full o and back to full on. This is where the switching losses come from.

A class E power amplier (PA) architecture maximizes amplier eciency by min-imizing the transistor switching losses. The general term for the switching behavior of a class E PA is called zero voltage switching (ZVS), meaning that the power transistor switches on and o only when the drain voltage is at 0 Volts potential. The PA achieves ZVS by using as its output load a tuned LC resonant circuit which is tuned to resonate at the switching frequency. The step response into an undamped resonant load causes ringing, and by switching the transistor only at the zero crossings of the drain voltage caused by this ringing eect, the transistor switching losses can be eliminated.

The original inventor of the Class E amplier [28, 29], and more recent papers as well [30,31,32,33], all call for an RF choke to be used as the amplier's load. For this design, instead of using an RF choke, the load network of the PA uses a parallel LC tuned tank circuit. The tuned circuit elementsLp and Cp make up a parallel resonant LC circuit, and such circuits have very high impedance (theoretically Z =∞+j0) at ω0 = 1/p

LpCp and low impedance at all other frequencies.

Using a tuned LC network as the amplier load has several benets, making it a much more attractive load than a simple RF choke. All of these benets arise from the singular fact that using a tuned LC network makes it possible to have a very large load impedance while using a much smaller load inductance than what would be necessary when using an RF choke. The benets to using a smaller valued inductor in the PA are several fold such as:

• Smaller inductance values require smaller package sizes

• Smaller inductors need fewer windings which reduces the inductor's parasitic series resistance and parallel capacitance

VDD

RL

C_s Ls

Cp Lp

Figure 7.1: The class E power amplier architecture used in this project.

• Smaller inductors need fewer windings which reduces the inductor's series resis-tance

• Smaller inductance with less parasitic capacitance results in higher self resonant frequencies

Another critical point where a smaller load network inductor helps is that power MOSFETS have an intrinsic output capacitanceC_oss ≈C_ds+C_dg, where

C_ds+C_dg

are the MOSFET drain-source and drain-gate capacitance. A power MOSFET's C_oss can easily be several hundred picofarads, and if C_oss is larger than the parallel load capacitance called for by the standard set of design formulas (7.3) then that particular MOSFET cannot be used in the tuned amplier. In addition to this, C_oss is very C_ds dependent, andC_dsis proportional to the drain voltage, causing the amplier's behavior to change as the transistor's drain voltage oscillates up and down. Using a resonant load network helps with these problems because as the inductance gets smaller, the required resonant capacitance gets larger making it fairly easy to have C_p > C_oss. As C_p is made larger, then the drain voltage induced variations toC_oss will have less of an impact on the amplier's resonant tuned output. In general, throughout the duration of the project, there were no occasions where it would have been preferable to use an RF choke as the load impedance.

7.1.1 Designing and Tuning the Power Amplier

Almost any design reference on the class E amplier gives a list of explicit design equations full of design factors which are derived by directly solving the amplier under dierent operating conditions [28,29,30,31,32,33]. To illustrate this point, the class E explicit design equations from [29] are given in (7.1) through (7.5),where V0 is the MOSFET drain source voltage when it is switched on,QLis the network quality factor, ESR is the parasitic electrostatic resistance of the respective reactive component, R_L is the PA output impedance,R_on is the MOSFET on resistance, tf is the MOSFETV_ds fall time, and T is the 1/f period

QL−0.104823 1.00121 + 1.01468 QL−1.7879

The design method presented here does not use these explicit design equations.

Instead, a more intuitive design method, based entirely on the desired PA output impedance and quality factor, is used to choose the reactive components. The PA in Fig. 7.1has a parallel LC network as its load with a series LC output network, and both networks have a resonant frequency ω₀ = 1/√

LC. The PA is tuned when the series network, Ls and Cs, is tuned to a resonant frequency ωs =ω0−∆ω/2, and the parallel network, Lp and Cp, is tuned to ωp = ω0 + ∆ω/2. For this design method, knowing the exact value of ∆ω before constructing the amplier is not too critical. A circuit design simulator, such as Spice [34], can be used to nd the required ∆ω. But, in a real life environment, it is much quicker to place the reactive component values withω_s=ω_p =ω₀, and to then simultaneously tuneω_sto a lower frequency, and ω_p to higher frequency using trimmer capacitors or inductors until the drain voltage operates with the desired zero voltage switching.

Starting with the PA Fig. 7.1, a desired Q_L, R_L, and operating frequency f, the design process proceeds as follows:

1. Choose a value for Q_Lbased on the design requirements.

- QLis usually chosen to be a value somewhere between 3 and 20.

- A higherQLhas sharper bandpass ltering resulting in less sideband energy.

- Lower QL ampliers were usually easier to tune.

2. Choose an amplier output impedance (7.6) based on the available supply voltage and desired output power¹.

- Lower R_L delivers more power using lowerV_dd

- Higher R_L requires less load current for the same output power resulting in less power loss to the PA's parasitic resistances.

3. Choose a nominal value forL_s (7.7), C_s (7.8), andL_p (7.9).

- Choosing Lp is a fairly non-critical step because a very wide range of values are acceptable, and it was only necessary thatL_p < L_s/2.

- Eq. (7.9) was shown to be eective for 2≤Q_L≤30 4. Choose a nominal value forCp (7.10).

5. Trim, simultaneously, the parallel load to a higher resonant frequency, and the series network to a lower resonant frequency untilωp−ωs = ∆ω. An oscilloscope is used to determine when ωp−ωs = ∆ω as this is the point where zero voltage switching is achieved.

1 The PA output power is not exactly given by (7.6). The eective supply voltage seems to be reduced as the quality factor is increased, but even with this scaling, the PA output power is still a function of the square of the supply voltage

R_L= ^dd

P (7.6)

Ls= QLRL

ω0 (7.7)

C_s= 1

ω₀²Ls (7.8)

Lp = Ls

2√

QL (7.9)

C_p = 1

ω₀²Lp (7.10)

There are no real requirements for the parallel network ωp and serial network ωs to be equally spaced above and below ω₀. Instead, it is only necessary that ω_s < ω₀ and ω_p > ω₀, and that ∆ω is large enough to achieve zero voltage switching as in Fig 7.3a.

On the practical side of the design process, trimming the ω_s and ω_p resonant fre-quencies was performed using trimmer capacitors instead of trimmer inductors. This is because it was easier to nd high voltage, temperature stable, mica lm capacitors with a wide adjustment range than it was to nd high current, high frequency, inductors which could be tuned across a wide range.