12. Conclusion & Future Topics
During the coarse of the work a modified three-line Marchand balun topology was investigated which helps in reducing the phase velocity difference between even and odd modes. The result is an improvement in insertion loss and amplitude imbalance over a wider frequency range.
Based on the proposed approach a WR-06 band and a WR-03 band balun was designed, 3D-EM simulated, and measured, showing good correlation.
A novel architecture of a WR-03 band receiver based on a sub-harmonic approach was proposed and implemented. The topology comprised of a stacked gilbert-cell switching quad fed by in-phase LO signals. The circuit demonstrated state-of-the-art CG bandwidth. In addition to this work, a WR-06 band fundamental down-conversion mixer based on the conventional Gilbert-cell approach was designed. A wideband performance was achieved using a similar matching network topology as presented for the WR-06 wideband amplifier.
One of the highlights of the thesis was the proposition and realization of a novel method of maximizing the output power and efficiency of mm-wave and terahertz signal sources which are based on the push-push topology. This method involves introduction of a common-mode parallel resonance at the desired second-harmonic signal and demonstrated an output power improvement by more than 6 dB as compared to conventional approaches. Two 0.3 THz VCOs were realized showing state-of-the-art performance. Another VCO working in the WR-06 band based on a fundamental Colpitts topology was designed aiming to achieve a high output power and wide tuning range. The work also includes the design and implementation of a 0.3-THz frequency doubler chip providing a high CG and 3-dB bandwidth of 50 GHz.
Towards the conclusion of the thesis a WR-03 band radar sensor in an eWLB package was designed with a push-push 240-GHz frequency doubler and a sub-harmonic receiver. Alhough, the complete functionality of the radar could not be demonstrated at the package level, more success was achieved for the WR-03 AiP. The motivation for the AiP was to investigate and find an antenna topology capable of providing wide input impedance and gain bandwidth in an eWLB package environment. In this regard, a CPW-fed slot bow-tie antenna was designed providing a measured gain bandwidth from 228−252 GHz with a peak gain of around 4.2 dBi.
Further investigations showed that at these frequencies, a successful design requires that the antenna, the reflector at the backside of the package, and the package dimensions must be co-designed.
12.2 Ongoing and Future Topics A 360-GHz VCO employing common-mode impedance enhancement In order to further investigate the efficacy of the technique employed to improve efficiency of push-push based oscillators introduced in Chapter 9, another VCO was designed and implemented in IHP’s SG13S technology. The target was to achieve an oscillation frequency higher than 350 GHz. The primary change compared to the previous version of the VCO was to extract the desired second harmonic signal from the common-mode junction at the base of the core HBT devices. In this topology no inductors are required at the collector terminals and there are overall less parasitics which helps to increase the resonant frequency. However, this topology provides no isolation between the load and core resonant circuit. Preliminary measurements showed that the VCO operated upto a peak resonant frequency of 360 GHz.
A fully-differential WR-03 band transceiver with higher output power One of the short-comings of the radar transceiver presented in Chapter 11 was that the output of the transmitter was single-ended which compelled to use a single-ended antenna. In order to use identical antennas at both TX and RX side, a balun had to be used for the differential down-conversion receiver. The loss incurred at this balun, however, directly adds to the NF and degrades the CG of the receiver chain. In the next version of the radar transceiver, this short-coming was avoided by using two push-push based frequency doubler fed by quadrature differential signals. Consequently, the output of the two frequency doublers are 180◦ out of phase thereby producing a differential signal at the RF pads. The same fully-differential sub-harmonic down-converter was used at the receiver. Furthermore, improvements were made in the LO distribution, biasing, supply bypassing and decoupling. The transciever chip has a size of 3 mm×3 mm and is intended to be packaged in eWLB.
WR-03 band differential bow-tie AiP Following the same lines as the single-ended CPW-fed bow-tie antenna, a differential bow-tie antenna was designed. Simulations in CST showed an improved beam pattern symmetry and reduced ripple in radiation pattern as well as over frequency.
Thus, eventually it can be argued based not only on the presented work but envisioning the rapid progress in integrated circuit and mm-wave packaging technology, that the future entails high resolution radar sensors in package working at sub-mm-wave frequencies enabling the demands of the fast-approaching autonomous era.
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List of Figures
1.1 (a) Schematic diagram of the first point-contact transistor. It was connected in a common base (CB) configuration, with emitter terminal connected to a positive direct current (d.c.) voltage, generating holes in a surface layer (the p-type inversion layer). The holes get swept by the negative voltage at the collector, producing an amplified signal at the load. (b) The first junction transistor (npn) biased in an amplifier configuration on a single Ge crystal. . . 5 1.2 The first IC (size: 1.6 mm ×11.1 mm), containing a single transistor, several
resistors and a capacitor on a slice of Ge, interconnected using “flying wires” of gold. Picture courtesy Texas Instruments Incorporated. . . 6 2.2 Variation of small-signal common-emitter (CE) current gain (β(ω)) and
maxi-mum available gain (MAG) as a function of frequency and the definitions of cut-off frequency (fT) and maximum oscillation frequency fmax. In practical cases, MAG(f) does not exhibit a region of constant slope and cannot be accu-rately extrapolated. Instead, unilateral gain (U(f)) is used, which typically has a very close x-axis intercept to MAG(f). . . 16 2.3 High-frequency equivalent small-signal hybridπ-model for calculating fT. . . . 17 2.4 High-frequency equivalent small-signal hybrid π-model including the series
parasitic resistances, Early resistance, and the collector-emitter capacitance.
This model, although still very simple, is comparatively accurate for calculating power gain and input impedance at mm-wave frequencies. . . 18 2.5 Calculation of high-frequency output impedance based on an equivalent
small-signal hybridπ-model for derivation of fmax. . . 19 2.6 Calculation of high-frequency output impedance based on an equivalent
small-signal hybridπ-model for derivation of fmax. . . 20 2.7 Simplified noise equivalent circuit of a high-frequency bipolar transistor. Noise
sources are shown in gray. . . 21 2.8 A linearly graded Ge base profile for a SiGe HBT. Also shown are the energy
band diagrams of a Si BJT and a SiGe HBT. The Ge grading results in a larage built-in pseudopotential which greatly reduces the base transit time for electrons. 23
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2.9 Variation offT,fmax and NFmin as a funtion of collector current density. The corresponding current densities for optimum fT, fmax and NFmin are also annotated. . . 27 2.10 Simplified SiGe HBT layout configurations (a) BEC, (b) CEBEC, and (c) CBEBC. 28 2.11 Simplified representation of a double poly silicon self aligned
(DPSA)-non-selective epitaxial growth (NSEG) architecture employed for the Dot7 IHP SiGe HBTs. Based on [80]. . . 31 2.12 Benchmark SiGe HBT technologies. Each marker shows the abbreviation of the
semiconductor manufacturer and the year in which the results were published.
Both Dot5 and Dot7 achieved record values. . . 32 2.13 (a) Layout of IHP’s SG13S high-speed HBT device with a CBEBC configuration
showing the interdigitated structure. (b) Interconnect aluminum layers from Metal 1 (M1) to Thick Metal 2 (TM2) of IHP’s SG13S process, drawn to scale.
Vias are not shown for simplicity. . . 33 2.14 Simulated plots of IHP’s SG13S high-speed HBTs. (a) MAG of HBTs biased
at peak-fT current density and (b)fT/fmax. The HBTs are 0.17×2×4µm2 and 0.17×2×5µm2 in size. Plots include the effect of parasitics up to the TM2. . . . 33 2.15 Cross-sectional view of the accumulation-depletion mode differential MOS
varactor available in IHP’s SG13S process. . . 34 2.16 Simulated and measured characteristics of IHP’s SG13S MOS varactor. (a) Capacitance.
(b)Q-factor. (c) SimulatedQ-factor at different control voltages. . . 34 2.17 (a) Simulated plots offT/fmax of IFAG B11HFC high-speed HBTs. The HBTs
have an emitter mask size of 0.22×2.8µm2. (b) Interconnect copper layers from Metal 1 (M1) to Metal 6 (M6) of IFAG B11HFC process, drawn to scale. Vias are also shown. . . 35 3.1 Simple amplifier models based on (a) distributed circuit design and (b) lumped
circuit design. . . 41 3.2 Lumped circuit based broadband amplifier architectures. (a) Resistive Feedback.
(b)fT-doubler technique with shunt-feedback Darlington pair. (c) Cherry-Hooper stage with EF Feedback. (d) EF and degenerated Cascode stage. . . 42 3.3 High-frequency equivalent-circuit model for the CB amplifier used as the input
stage when capacitively loaded. RC consists of parallel combination of collector and load resistance. . . 43
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3.4 (a) Effect of rB on the voltage gain of the CB amplifier when gm is assumed to be frequency independent. Value of rB is varied from 0 Ω to 30 Ω in 10 Ω steps. Dashed blue lines and solid black lines are forCL= 1 fF and CL= 20 fF, respecitvely. (b) Effect of CL on voltage gain of the CB amplifier when rB is assumed to be zero. Value of CL is varied from 10 fF to 30 fF in 5 fF steps.
Dashed blue lines and solid black lines assumegm is frequency-dependent and frequency-independent, respectively. . . 45 3.5 (a) Effect of CLon the cut-off frequency of the voltage transfer function of the
CB amplifier (Here, the cut-off frequency is defined as the point where the voltage gain becomes equal to 0 dB). Dashed blue line and solid black line assume gm is frequency-dependent and frequency-independent, respectively. (b) Effect offT on voltage gain of the CB amplifier whenrB is assumed to be 0 Ω. Value of fT is varied from 350 GHz to 200 GHz in 50 GHz steps. . . 46 3.6 Effect ofrB on real and imaginary part of input impedance of the CB amplifier
at 100 GHz, whengm is 400 mS. . . 47 3.7 (a) Effect ofgmon real part of input impedance of the CB amplifier when assumed
to be frequency dependent (solid black line) and frequency independent (dashed blue line).rB is 5 Ω. (b) Effect ofgm on imaginary part of input impedance of the CB amplifier when assumed to be frequency dependent (solid black line) and frequency independent (dashed blue line). “ωcr" is the frequency point where
=(Zin) crosses zero and becomes capacitive. “jωL" is a guide line showing a constant inductive-reactance.rB is 5 Ω andgm0 is 40 mS. . . 48 3.8 (a) Effect of rB on imaginary part of input impedance of the CB amplifier when
gm is dependent upon frequency. Value of rB is varied from 0 Ω to 15 Ω in 5 Ω steps. It can be seetn that the “ωcr" points are not strongly dependent on the values ofrB.gm0 is 40 mS. (b) Effect offTon imaginary part of input impedance of the CB amplifier whenrB is assumed to be zero.fT is varied from 200 GHz to 300 GHz in 50 GHz steps, gm0 is 40 mS. . . 49 3.9 High-frequency equivalent-circuit model for the emitter follower when
capaci-tively loaded.RS consists of series combination of transistor’s base resistancerB
and the source resistance.Req consists of parallel combination of load resistance RL and emitter resistance RE. . . 50 3.10 Voltage gain of the EF. Dashed blue line and solid black line assume gm is
frequency-independent and frequency-dependent, respectively. The peak gain frequency isωr. The magnitude of the peak gain is proportional to gm0. . . 51 3.11 Effect of CL on voltage gain of the EF with a capacitive load. The resonant
frequencyωr increases with decreasing value ofCLwhereas magnitude of peak gain is directly proportional to CL. . . 53
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3.12 Increase in the resonant frequency ωr with increase in the inductive part of the output impedance of the preceding EF stage. . . 53 3.13 (a) Real part of the input impedance of the EF under different capacitive loads.
At higher values of CL, the real part can become negative. C1, C2, C3 and Req are 5 fF, 15 fF, 30 fF and 50 Ω, respectively.(b) Imaginary part of the input impedance of the EF under different capacitive loads. . . 54 3.14 Circuit diagram of the differential broadband amplifier showing the input CB
stage, the 4 cascaded EFs, output cascode stage and the cascode-connected current mirrors used for the biasing. . . 56 3.15 (a) Simulated real and imaginary parts of the input impedance of the CB stage
of the proposed amplifier when capacitively loaded. The agreement with the analytical graphs in Fig. 3.7(a) and Fig. 3.7(b) can be observed.(b) Simulated real and imaginary parts of input/output impedance of different stages of the proposed differential broadband amplifier. The positive resistance of the CB stage (dashed-blue line) compensates the frequency dependent negative resistance of the EFs (black dashed-dotted line) to provide an overall positive and relatively constant input resistance (solid red line). . . 57 3.16 (a) Simulated voltage and power gain of different stages of the proposed
differ-ential broadband amplifier. The solid red line shows the overall improvement in voltage-gain provided by the CB input stage which also improves the stability of the circuit.(b) Simulated stability factor K of the proposed fully-differential amplifier. . . 58 3.17 Micrographs of the fabricated broadband amplifiers. The DC-pads are not shown.
Each RF-pad size is 50µm x 50µm. (a) Differential-ended version with a core area of around 160µm x 100µm. (b) Single-ended version with a core area of around 160µm x 80µm. . . 59 3.18 Measured small-signal results. (a) S-parameters of differential broadband
ampli-fier showing a 3-dB bandwidth of 105 GHz and an input RL better than 10 dB throughout DC−110 GHz.(b)µ-factor and group delay (GD) of the differential broadband amplifier. (c) S-parameters of the single-ended broadband ampli-fier showing a 3-dB bandwidth of 91 GHz and an input RL better than 10 dB throughout DC−87 GHz. (d)µ-factor and GD of the single-ended broadband amplifier. . . 60 3.19 (a) Measured power-gain and Pinvs Poutof the single-ended broadband amplifier
at 85 GHz. The curve shows an OP1dB of 1.2 dBm and aPsat of 2.5 dBm.(b)Psat
of the single-ended broadband amplifier measured across W-Band. . . 61
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4.1 (a) High-frequency equivalentπ-model of the the cascode stage with the proposed output interstage broadband matching network.(b) Model for calculating the transimpedance transfer function. (c) Simplified model when the CB base current and ro is ignored. . . 64 4.2 (a) Transimpedance-gain of the CB stage when matched to the next CE stage
plotted using the high-frequency analytical model (cf. Fig 4.1(b)), the simplified model (cf. Fig 4.1(c) and (1)) and Spectre RF simulations. (b) SimulatedCµ and Cπ of the high-frequency HBTs as a function of their device size. The effective emitter-width is kept constant at 0.13µm while the emitter-length is varied (1µm, 5µm, 10µm, 7×2µm and 10×2µm). (c) The analytical plots for the variation of the transimpedance-gain over frequency as a function of device size of the CB-stage (Cµ1), size of CE-stage is 0.13×10µm2 and, (d) the CE-stage (Cπ2), size of CB-stage is 0.13×10µm2. . . 66 4.3 Schematic of the D-band broadband PA . . . 68 4.4 (a) Simulated transimpedance-gain of the individual stages (calculated from
the CB stage to the input of the next CE stage) of the D-band broadband amplifier. (b) Combined power-gain profiles of the amplifier emphasizing the effect of staggered-gain tuning. . . 69 4.5 (a) Layout design of first two cascode stages of the PA in Sonnet.(b) Perspective
view of the D-band modified Marchand balun simulated in CST®. . . 70 4.6 Chip micrographs. (a) Differential D-band broadband PA with integrated baluns.
Chip size including pads: 0.7×0.6 mm2. (b) D-band wideband modified Marchand balun. Chip size including pads: 0.425×0.4 mm2. . . 71 4.7 Small-signal measurements (solid lines) and simulations (dashed lines). (a) Insertion
loss and input reflection coefficient of the modified Marchand balun. (b) Small-signal gain and NF of the PA. (c) Input/output reflection coefficients and isolation of the PA. (d)µ-factor and GD of the PA. . . 72 4.8 Large-signal measurements (solid lines) and simulations (dashed lines). (a) Saturated
output power and 1-dB output compression point of the PA versus frequency at a constant 2.7 V supply. (b) Output power, power-gain, and PAE of the PA as a function of input power at 160 GHz. (c) Saturated output power, and (d) PAE, as a function of supply voltage and two different biasing conditions adjusted for optimal power efficiency (Bias 1) and optimal output power (Bias 2) at 160 GHz. 73 5.1 (a) A backward-wave coupler with identical port terminations. (b) Schematic
of a conventional symmetric two line Marchand balun with widthsa1 anda2. (c) Schematic of a symmetric three line modified Marchand balun with widths
b1, b2,b3, and an air bridge. (d) Cross section and equivalent representation of the coupled line shown in (b). (e) Cross section and equivalent representation of the coupled lines shown in (c). . . 77
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5.2 Variation of coupling to the direct (S21 −shown by dashed lines) and coupled ports (S31 −shown by solid lines) in dB of a quasi-TEM type backward-wave coupler for a nominal coupling factor of 3 dB for different values of r, where r is the ratio of even- and odd-mode phase velocities. (a)r = 1, (b)r = 0.75, (c)r = 0.5 and (d)r= 0.25. . . 78 5.3 Variation of sum of power transfer ratios to ports 2 and 3 in dB of a quasi-TEM
type backward coupler for nominal coupling of 3 dB for different values of r. . . 79 5.4 Calculated S-parameters of the Marchand balun with a coupling factor of
−4.8 dB for different values ofr. (a)r = 1, (b)r= 0.75, (c)r = 0.5, (d)r = 0.25. 80 5.5 Calculated (a) insertion loss and (b) amplitude imbalance of the Marchand balun
at ff
c = 1 for different values of r. . . 81 5.6 Perspective view of the modified Marchand balun. . . 82 5.7 Micrographs of the fabricated Marchand baluns in SiGe. (a) Single balun with
integrated fuses. (b) Back to back balun. . . 82 5.8 (a) Measured and simulated insertion loss and (b) Measured (solid lines) and
simulated (dotted lines) input and output reflection coefficients of the fabricated modified Marchand balun. . . 83 5.9 Measured (solid lines) and simulated (dotted lines) (a) amplitude imbalance
(b) phase imbalance of the fabricated modified Marchand balun. . . 83 6.1 Wideband down-conversion mixer with integrated LO buffer and input/output
LC baluns. (a) Without RF amplifier.(b) With RF amplifier. . . 88 6.2 Schematic of the double-balanced down-conversion mixer with IF buffers. . . . 89 6.3 Simulated input/output reflection coefficients, CG, and SSB NF of the mixer
shown in Fig. 6.2. LO power is 0 dBm. . . 90 6.4 Chip micrographs. (a) Mixer and 3-stage LO buffer. Chip size: 980µm×730µm.
(b) Mixer, 3-stage LO buffer, and 2-stage RF amplifier. Chip size: 1200µm× 730µm. . . 91 6.5 Measured and simulated CG of the mixer at 155 GHz (IF = 1 MHz) as a function
of LO buffer output power (mixer core input). . . 92 6.6 Measured CG and output IF power of the double-balanced mixer at 155 GHz
(IF = 1 MHz) as a function of RF input power. LO power at the mixer-core input is around 0 dBm. (a) Without RF amplifier (b) With RF amplifier. . . 92 6.7 Measured CG of the receiver in D-band at an IF frequency of 1 MHz. The CG
drops at the lower end of the D-band primarily due to the limited bandwidth of the LO buffer. . . 93 7.1 Architecture of the receiver chip with wideband LO and RF Marchand baluns,
LO amplifiers, and a subharmonic mixer. . . 96
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7.2 (a) Simplified Gilbert cell multiplier. (b) Gilbert cell multiplier functioning as a phase detector if both v1 andv2 are large as compared to VT. Ifv1 and v2 have the same frequency but a phase difference of 90◦, the frequency of the output signal is doubled. . . 96 7.3 Circuit schematic of the subharmonic mixer with integrated IF buffers. . . 98 7.4 (a) Simulated input reflection coefficients of the subharmonic mixer core at the
RF, LO, and IF ports. (b) Simulated CG and the IP1dB of the mixer core as a function of the LO power at 240 GHz. . . 99 7.5 Simulated results of the subharmonic mixer over frequency plotted for three
different LO powers,(a) CG and (b) NFDSB. . . 99 7.6 Layout of the subharmonic mixer simulated in Sonnet. . . 100 7.7 Micrograph of the subharmonic receiver. The dimensions of the entire chip are
0.9×0.6 mm2. The mixer occupies only 160×160µm2. . . 100 7.8 Setup for measuring CG of the J-band subharmonic mixer . . . 101 7.9 (a) Measured CG and NFDSBof the receiver chip over frequency for two different
supply voltages. IF frequency is 100 MHz. LO power drops considerable after 140 GHz leading to the drop in CG. (b) Measured (solid) and simulated (dotted) CG and output power of the receiver chip versus the RF input power at 280 GHz.
IF frequency is 100 MHz. IP1dB could not be reached because of insufficient RF power. . . 101 7.10 Measured output power of the two stage integrated LO amplifiers over frequency.102 7.11 Measured CG of the subharmonic mixer as a function of the LO power at the
receiver input pads (a) at 240 GHz and (b) 280 GHz. . . 102 8.1 Differential mm-wave VCO topologies. (a) Conventional Colpitts VCO. (b) Colpitts
VCO with differential varactor tuning. (c) Colpitts VCO with capacitor cross-coupling. (d) Colpitts-Clapp VCO. (e) Colpitts VCO with variable inductance.
(f) Modified Armstrong VCO. (g) Conventional cross-coupled VCO. (h) Transformer-based cross-coupled VCO. . . 108 8.2 Schematic of the fully-differential Colpitts VCO including the parasitics of the
RF-transistor contacts, Rpar and Lpar. . . 110 8.3 (a) Micrograph of the VCO with two GSG RF-pads for characterizing each
of the differential ports using a single-ended measurement setup. The size of the chip is 0.37 mm x 0.28 mm. (b) Micrograph of the VCO with an integrated LC-balun for performing single-ended measurements. The size of the chip is 0.28 mm x 0.38 mm. . . 111 8.4 (a) Measured tuning characteristics of the VCO for three different supply
volt-ages. It covers a tuning range of almost 12 GHz at a supply voltage of 3.3 V.
(b) Measured VCO output power at three different supply voltages. For 3.3 V supply a maximum output power of 9 dBm is achieved. . . 112
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8.5 (a) Measured phase noise performance of the VCO over tuning frequency at 1 MHz and 10 MHz offset when operated at a supply voltage of 3.3 V..(b) Measured phase noise plot of the VCO over offset-frequency. The carrier frequency is 154.4 GHz and the VCO is operating at a supply voltage of 3.3 V.. . . 113 8.6 Measured power spectrum of the free-running VCO at 156.7 GHz at a supply
voltage of 3.3 V. . . 113 9.1 (a) Simplified lumped element circuit of a differential Colpitts oscillator based
push-push VCO. The dashed-blue line shows the proposed common-mode resonant capacitor Cr. (b) High-frequency equivalent even-modeπ-model of the VCO half-circuit shown in (a). (c) Simplified equivalent circuit for calculating the input impedance Zin (without Cr) and Zin0 (withCr). (d) Equivalent input-impedance of the circuit depicted in (c), with and withoutCr, showingReff and Ceff. . . 119 9.2 Calculated plots of effective resistance (Reff) and effective capacitance (Ceff) as
a function of frequency. . . 122 9.3 Analytical and simulated plots of the input reactance of the push-push VCO,
as seen from the base terminal. (a) No Cr is used. (b) An optimized value of Cr
is used for common-mode impedance enhancement. . . 122 9.4 Analytical and simulated plots of the input resistance of the push-push VCO,
as seen from the base terminal. (a) No Cr is used. (b) An optimized value of Cr is used for common-mode impedance enhancement. . . 123 9.5 Schematic of the push-push VCO. The contact parasitics denoted byLpar and
Rpar are also shown. . . 125 9.6 Simulated input impedances as seen from the portsZD andZCMfor the designed
THz VCO. The fundamental resonance can be seen at 150 GHz with a negative resistance of around −160 Ω and a common-mode resonance achieved using an optimized value of Cr, is found at around 300 GHz. (a) Imaginary part. (b) Real part. . . 126 9.7 Simulated load-pull power contours to findZoptfor the 0.3 THz VCO. (a) Conventional
design without usingCr. The constant power contours are plotted from−12 dBm to −6 dBm with a 1 dB step. Popt is −5 dBm. (b) Proposed design using an optimum value ofCr for common-mode impedance enhancement. The power contours are plotted from −10 dBm to 0 dBm with a 1 dB step.Popt is +1.7 dBm.127 9.8 Simulated plots of the VCO. (a) Voltage swing at the load RL, without and
with an optimized value ofCr. (b) Fundamental and second harmonic output power at the load as a function of Cr. . . 128 9.9 (a) Simulated tuning characteristics of the VCO without and with an optimized
value ofCr. (b) Output power of the optimized VCO for each tuning frequency as a function of Cr. . . 129
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9.10 Frequency pulling and phase noise as a function of Cr at a tuning voltage of 3 V. The phase noise is plotted at an offset of 10 MHz. . . 129 9.11 The VCO2 core layout shows the via stack of the HBTs, MOS varactor, MIM
capacitors, and the microstrip transmission lines implemented on TM2. . . 131 9.12 (a) Micrograph of VCO1. Total chip area is 0.3 mm2. (b) Close-up view of
micrograph of VCO2. DC pads are not shown. The active chip area is around 0.05 mm2. . . 131 9.13 On-wafer measurement setups for the VCO chips. (a) Frequency and phase noise
measurements employing R & S frequency converters and Keysight signal source analyzer. (b) WR-03 band power measurement employing Erickson’s PM4 power meter. . . 132 9.14 Measured tuning characteristics of the VCO chips at a supply voltage of 3.3 V. 132 9.15 Measured output power of the VCO chips at different supply voltages as a
function of the tuning voltage. (a) VCO1. (b) VCO2. . . 133 9.16 Measured phase noise performance of the VCO chips at a supply voltage of
3.3 V. (a) Phase noise plot versus the tuning voltage. (b) Phase noise plot versus offset-frequency at a tuning voltage of 6 V. . . 133 10.1 Architecture of the frequency doubler chip with integrated LC balun and
wideband amplifiers. . . 138 10.2 Circuit schematic of the push-push based frequency doubler. . . 138 10.3 Simulated input and output reflection coefficients of the frequency doubler. . . 139 10.4 Simulated results of the frequency doubler, (a) output power of the frequency
doubler over frequency, and (b) conversion loss and output power versus input power. . . 139 10.5 (a) Layout of the frequency doubler simulated in Sonnet. (b) Micrograph of the
frequency doubler chip. The dimensions of the entire chip are 0.98×0.58 mm2. 140 10.6 Measurement and simulation results of the D-band amplifier cut-out at a supply
voltage of 3.3 V. (a) Small-signal gain, and (b) input/output reflection coefficients and reverse isolation. . . 141 10.7 Measurement and simulated saturated output power of the D-band amplifier
cut-out. . . 141 10.8 Measured and simulated results of the frequency doubler chip. (a) Saturated
output power versus frequency. (b) Conversion gain and output power at 270 GHz as a function of power applied at the input pads. . . 142 11.1 Cross section of an eWLB package with an embedded MMIC soldered on top
of a standard PCB. The figure shows the different dielectric layers, the RDL layers, and as well as the solder and thermal balls. Figure updated and used with permission from [233]. . . 150
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11.2 Simplified block level diagram of the WR-03 band radar sensor in package. The colors represent the different hierarchical levels at the MMIC, eWLB package, and the PCB. . . 152 11.3 (a) A finite biconical antenna with an input impedance Zi,bc, characteristic
impedanceZo,bcand an equivalent load impedanceZLat the imaginary boundary sphere. (b) Equivalent transmission line representation of a finite biconical antenna.153 11.4 Geometry of the proposed WR-03 band slot CPW bow-tie antenna. The design
parameters of the antenna are annotated. . . 154 11.5 Perspective view of the TX and RX CPW bow-tie antenna in eWLB package. The
slot antenna is designed in RDL 1 and the backside metallization is manufactured using RDL 2. The embedded TRX chip can be seen in the right-hand side figure.155 11.6 Simulated realized gain of the bow-tie AiP at 240 GHz. The antenna gain does
not include the loss of the transition from the MMIC pads to the RDL layer. . 155 11.7 Simulated realized gain and input reflection coefficient of the bow-tie AiP as a
function of frequency. . . 156 11.8 Simulated radiation pattern of the bow-tie AiP. (a) H-plane. (b) E-plane. . . 156 11.9 Perspective view of eWLB packages with two different sizes but identical antenna
dimensions to investigate the influence of package size on AiP performance. The package with a size of 4 mm×4.7 mm is optimized for the desired performance. 157 11.10Influence of package dimensions on realized gain and radiation pattern at
differ-ent frequencies by considering two differdiffer-ent package sizes, (i) Size A: 4 mm×4.7 mm which is the optimized dimension, shown on the left hand side, and (ii) Size B:
6 mm×6 mm which is a standard eWLB package size, shown on the right hand side. (a)−(b) 230 GHz. (c)−(d) 240 GHz. (e)−(f) 250 GHz. . . 158 11.11Photographs of the J-band eWLB radar sensor with the bow-tie AiP. Size of
the package and the embedded chip is 4.7 mm×4.0 mm and 3.0 mm×1.44 mm, respectively.(a) Bottom side. (b) Top side with a backside metallization at RDL 2 with a window opening of 2 mm×0.95 mm. . . 160 11.12Measured radiation patterns of the J-Band AiP at three different frequencies.
(a) H-plane. (d) E-plane. . . 161 11.13Measured gain of the J-band AiP at θ= 0◦. The gain includes the loss of the
chip-to-package transition. . . 161
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