ALPHA 16 AND NAKED MINI 16 INSTRUCTIONS 2.1 INTRODUCTION
2.4 MEMORY REFERENCE INSTRUCTIONS: BYTE MODE
2.4.1 General
When the ALPHA 16 or NAKED MINI 16 computer is set for Byte Mode processing, Memory Reference instructions perform their logical or airthmetic operations using byte operands instead of word operands. When in Byte Mode, all of the memory reference instructions use byte operands with four exceptions: JMP, JST, IMS, and SCN. Even in Byte Mode, these instructions use word operands.
2.4.1.1 Byte Operands. General concepts of byte mode processing are discussed in Part 1.3.9 of Section 1. Several important points are illustrated in that discussion:
1.
2.
3.
When a byte operand is read from memory, the byte is right justified within the operand word and the upper eight bits of the operand word are set to zeros.
Byte Mode affects the operand cycle only. Once the operand is read from memory, all other operations within the computer are performed the same as for full 16-bit words. In the case of byte operands, only the eight least significant bits of the operand word contain significant information.
A byte operand is an unsigned, absolute magnitude value for arithmetic operations; i.e., byte operands are always handled as positive values. This is true because the upper eight bits of a byte operand word always contain all zeros.
4. For arithmetic operations, carries are ~ndled
as if both values involved are full 16-bit words.
Overflow will be set only if an arithmetic opera-tion causes a full word arithmetic overflow; i.e., a carry from bit 7 to bit 8 of the Adder will not set the Overflow indicator. Overflow is set by the same conditions as for Word Mode.
5. Register store operations store the lower byte (eight least significant bits) of the register in the effective byte address.
2.4.1.2 Excluded Instructions. There are four memory reference instructions which are not affected by Byte Mode. These instructions always use a full word operand regardless of whether or not the computer is set for Byte Mode. The four excluded instructions are:
1. IMS
2. SCN
3. JMP
4. JST
IMS is normally used to incre-ment counters for loops and timers, or indirect addresses for stepping through tables. Byte operands for IMS would be a limitation rather than an asset.
Scan Memory is normally used for full word searches. It is used extensively in program debug operations when searching for program branches, etc.
The unconditional Jump instruc-tion generates an instrucinstruc-tion address rather than an operand address. Instruction addresses are always full word addresses.
The Jump and Store instruction performs an operand cycle when it stores the contents of the P Register in the effective address. The full value of the
•
2.4.2 Byte Addressing
P Register must be stored for the instruction to be meaningful, therefore this instruction is excluded from Byte Mode.
The ALPHA 16 and NAKED MINI 16 computers have a maximum memory capacity of 64K bytes (32K words). A 16-bit address is required to address the maximum memory capacity in Byte Mode. When the computer is set for Byte Mode processing, the computer assumes that all operand addresses presented to memory by byte processing instruc-tions are byte addresses. The computer assumes that the address is in the format shown in Figure 1-11.
2.4.2.1 Memory Reference Instruction Format. Fig-ure 2-4 illustrates the format of memory reference instruc-tions. The format for Byte Mode instructions is the same as for word mode instructions, except for the interpretation of the M Field of the instruction. There is nothing in the format of the instruction that distinguishes-a memory ref-erence instruction executed in Byte Mode from a memory reference instruction executed in Word Mode. The param-eter that causes the computer to address a byte operand rather than a word operand is the Byte Mode indicator. If the Byte Mode indicator is set, the computer addresses byte operands. If the Byte Mode indicator is reset, the computer addresses word operands.
2.4.2.2 Direct Byte Addressing. Direct memoryaddress-ing in Byte Mode is not the same as for Word Mode addressing. The interpretation of the M Field is handled differently. Direct addressing is specified when 1=0 (Bit 8=0). Direct memory addressing modes are explained below and are summarized in Figure 2-4: (Figure 2-S illustrates the memory areas covered by each addressing mode.)
M=OO Byte Operand in Scratchpad. The D Field of the instruction contains the address of the byte operand in the scratchpad area of memory:
Y{byte)={D)
Since the D Field contains only eight bits, the address will have the form:
Y{byte)=OOOO 0000 xxxx xxxx
(D) are right justified in the address word, and the total word is used as a byte address to memory.
Since an 8-bit address can address up to 2S 6 byte locations, direct Scratchpad addressing can address the first 2S 6 bytes in memory (contained in the first 128 words in memory).
M=OI, Byte Operand Relative to P, Forward. Relative M=11 addressing uses a word address in the P Register along with a word address in the D Field of the instruction to form the address of the word con-taining the byte to be addressed:
Y{word)={P)+ 1 +(D)
The address thus formed addresses the word, and the M Field of the instruction specified which byte in the word is to be used:
M=OI Byte 0 (left Byte) M=ll Byte 1 (right Byte)
It is important to note that the address generated by relative addressing is a word address rather than a byte address. The M Field of the instruction specifies which byte of the word is being addressed.
The address generated has the form:
{D)word = 0000 0000 xxxx xxxx (P)+1 word = Oxxx xxxx xxxx xxxx Y{word) = Oxxx xxxx xxxx xxxx Note. Byte addressing does not permit direct addressing relative to P, backward.
M= 10 Indexed. The byte operand address is formed by adding the byte address value in the D Field to the byte address value in the X Register.
Field OpCode M Field (Mode)
I Bit D Field
Addressing Modes:
MM I
Direct Addressing:
00 0 01 0 11 0 10 0
Indirect Addressing:
00 01
11
10
I REGISTER
16 14 13 12 11 10 9 B 3 2
D FIELD
... OP ;OOE ....
-1- L
INOIRECT TAG MODE CODEBits Definition
II-IS Operation Code. Defines the specific instruction.
9, 10 Mode Code. Used in conjunction with the Indirect Tag
8 0-7
Scratchpad
Relative to P, Forward; Byte 0 Relative to P, Forward, Byte 1 Indexed
AP in Scratchpad
AP Relative to P, Forward AP Relative to P, Backward AP in Scratchpad, Indexed
to define the memory addressing mode to be used.
Indirect Tag. Specifies direct or indirect addressing.
Address Field. Base address used to form byte operand address or address pointer address.
Y(byte)={D) Y(word)={P)+ 1 +(D) Y(word)={P)+ 1 +(D) Y(byte)={D)+{X)
AP{word)={D), Y{byte)={AP) AP{word)={P)+ 1 +(D), Y{byte)=(AP) AP{word)={P)-{D), Y{byte)={AP) AP{word)={D), Y{byte )=(AP)+{X)
Figure 2-4. Memory Reference Instruction Format: Byte Mode
BYTE WORD ADD RESS ,..-_ _ _ _ _ _ M_E_M_O_R_Y _ _ _ _ _ ._ .... ADD RESS
(X) + 255 ~ - - - (X) + 255 2 INDEXED: 256 BYTES
(M = 10) Y (BYTE) = (X) + (0) BYTE LOCATIONS (X) ~(X) + (D) WORD LOCATIONS (X)/2":«X) + (D))/2
(X) ~ - - - - - - ~ - - - - - - - (X)/2
2 UP) + 1 + 255) ~ - - - _. - (P) + 1 + 255 RELATIVE TO P1 FORWARD: 512 BYTES
(M = 01 : BYTEO, M = 11 : BYTE 1) Y(WORD)=(P)+1+(D) ..
BYTE LOCATIONS 2 ((P) + 1)-.. ·2 «P) + 1 + (D)) . WORD LOCATIONS (P) + 1~(P) + 1 + (0)
2 «P) + 1) I- - - - - - - - - - - - - - - - (P) + 1
:FF ~ - - - : 7F SCRATCHPAD: 256 BYTES
(M = 00), Y (BYTE) = (D) BYTE LOCATIONS 0~255
'WORD LOCATIONS 0~127
:00 ... ---.-~ : 00
Figure 2-5. Direct Memory Addressing: Byte Mode Y(byte )=(D )+(X)
The address generated has the form:
(D)byte = 0000 0000 xxxx xxxx (X)byte = xxxx xxxx xxxx xxxx Y(byte) = xxxx xxxx xxxx xxxx This mode of addressing forms a 16-bit address capable of addressing any byte in memory. Since the X Register may be easily incremented or decremented, this mode is especially useful for stepping through segments of memory where data is packed two bytes per word.
2.4.2.3 Indirect Byte Addressing. If 1=1 (Bit 8=0, Indirect addressing is used to address a byte operand.
Indirect byte addressing is limited to single level indirect addressing; i.e., there is only one indirect Address Pointer between the instruction and the byte operand.
For indirect byte addressing, the M Field of the memory reference instruction is interpreted the same as for indirect word addressing. The addressing mode specified by the M Field is used to form the address of an Address Pointer, AP, in memory. The address of the Address Pointer is a full word address, since the Address Pointer must have a full 16-bit capacity. The Address Pointer contains a btye address in byte address format. The byte address in the Address Pointer may be used directly as an effective
memory address, or it may be modified by the contents of the X Register. Figure 2-6 illustrates Indirect Byte addressing.
M=Ol Address Pointer Relative to P, Forward.
The value in the D Field of the Memory Reference instruction is added to the contents of P, + 1, to form the address of the Address Pointer:
The addressing modes used for Indirect Byte addressing are as follows:
M=OO Address Pointer in Scratchpad. The D Field of the Memory Reference instruc-tion contains the word address of an Address Pointer in Scratchpad:
AP( word )=(D)
The Address Pointer contains the byte address of the byte operand:
Y(byte)=(AP)
M=l1