The KIlO and KAlO are similar, even identical, to the KLlO in many respects, but their implementation is quite different: they have no micro- controller or microcode. They use the PDP-10 instruction set but not in its full variety as available in the KLlO: neither earlier processor can handle strings or double precision fixed point numbers; the KAlO has no capability for handling doublewords or performing double precision floating point arithmetic, although it does have instructions (retained on all KLlO and KIlO TOPS-10 systems) for assisting the software in doing double precision floating point in a special software format.
Figure 1.8 illustrates the organization of a DECsystem-10 based on either of the earlier processors. The processor handles its peripheral equip- ment directly over an in-out bus, there is no cache, there is a real time clock but no meters, and all memory is external. The extra four bits shown on address registers are applicable only to the KIlO. Both processors use an l&bit internal address providing a virtual memory of one section that is compatible with section 0 of the KLlO. But whereas the KAlO has a maxi- mum physical memory equal in size to its virtual memory, which is organ- ized by protection and relocation hardware, the KIlO has a physical ad- dressing capability equal to that of the KLlO (22-bit address, 4096K) and has paging hardware. The KIlO virtual address space is the same as that of a KLlO with the TOPS-10 Monitor, except that in executive mode the first 112K of memory is unpaged (and thus not available to the supervisor pro- gram), and the Monitor can define a so-called “small user” whose accessible space must lie within the virtual ranges O-37777 and 400000-437777. The KIlO has four fast memory blocks, of which hardware requires that the Monitor use block 0; the KAlO has only one block.
Both processors have manual operator consoles with facilities that are directly relevant to the programmer, although they are used mostly for manually stepping through a program to debug it. From the sense switches and the 36-bit data switch register DS, the program can read information supplied by the operator, and through the memory indicators MI, the pro- gram can display data for the operator. By means of the address switch register AS, the operator can examine the contents of, or deposit informa- tion into, any memory location; stop or interrupt the program whenever a particular location is referenced; and supply a starting address for the pro- gram. In these processors IR contains the entire left half of the current instruction word, i.e. eighteen bits rather than thirteen. The memory ad- dress register MA supplies the address for every memory access. In the arithmetic logic of the KAlO, there are only single length registers; but in
l-38 Introduction
the KIlO, AR and AD have Z&bit left extensions for double precision float- ing point. The KAlO has no trapping mechanism: arithmetic and stack overflow signal the program by way of interrupts. Individual processor dif- ferences relevant to user programming are listed in Appendix E.
Figure 1.8: DECsystem-10 Based on KIlO or KAlO
r
I
LI
I
I I I
MEMORY BUS CENTRAL
PROCESSOR
IN.OUT BUS
ARITHMETIC
I-
LOGIC IAD, AR. ETC) PRIORITY MI DS1
36INTERRUPT
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CONSOLE TERMINAL
l
PAPER TAPE READER
I
PAPER TAPE PUNCH
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DISK SYSTEM
Memory
The following table gives the characteristics of the various memories avail- able with the KIlO and KAlO. Modify completion is the time to finish a read-modify-write cycle after the processor supplies the new data. Times are in microseconds and include the delay introduced by ten feet (three meters) of cable. Fast memory times are for referencing as a memory loca- tion (l&bit address); when a fast memory location is addressed as an accu- mulator or index register, the access time is considerably shorter.
Introduction l-39
Read Write generally not worthwhile because of the extensive overlapping that speeds up core access. However, except in instructions that use two accumulators, storage of a memory operand in fast memory not’ only takes no time but actually decreases slightly the nonmemory time.
In a system with the greatest possible capacity, the largest KIlO ad- page mapping, responding to priority interrupts, or other hardware-ori- ented situations, are to locations in the process tables.
l-40 Introduction
KAlO Memory Allocation. The use of certain memory locations is defined by the KAlO hardware.
0 o-17 1-17 40-41 42-57 60-61
Holds a pointer word during a bootstrap readin.
Can be addressed as accumulators.
Can be addressed as index registers.
Trap for unimplemented user operations WUOs).
Priority interrupt locations.
Trap for remaining unimplemented operations: these include the unassigned instruction codes that are reserved for future use, and also the byte manipulation and floating point instruc- tions when the hardware for them is not installed.
140-161 Allocated to second processor if connected (same use as 40-61 for first processor). All information given in this manual about memory locations 40-61 for a KAlO applies instead to locations 140-161 for programming a second KAlO connected to the same memory.
In a user program the trap for a local UUO is relocated to locations 40 and 41 of the user area; a Monitor UUO uses unrelocated locations. All other addresses listed are for physical (unrelocated) locations.
Introduction 1-41