Unlike earlier processors, the KS10 has no special format for IO instruc- tions. Instead they are simply those instructions that handle the peripheral equipment, the console and memory status - although for consistency, they do have 1s in the left three bits. KS10 IO instructions are oriented toward Unibus-type devices, as all peripheral equipment in a DECSYSTEM-2020 is handled through Unibus adapters. There are twelve of these instructions, six each for manipulating full words and bytes, de- scribed here in terms of their general effects for handling external devices.
Information about external devices - individual instruction descriptions, IO addresses, etc. - is given in the device documentation (however memory status is defined in §4.8).
NOTE
Ordinarily the user has no use whatever for the instructions described in this section. In almost all cases, input and out- put is handled by the Monitor in response to user requests employing MUUOs and various software formats. For infor- mation on user procedures vis-a-vis Monitor handling of user IO requirements, the reader should refer to the appropriate Monitor Calls manual.
Programmers who do handle their own input-output should note that the instructions described here are in-out instructions, which are affected by the timeshare instruction restrictions. Namely an instruction of this type cannot be performed by a user program unless User In-out is set. Any in-out instruction that violates this restriction does not per- form the functions given for it in the instruction description.
Instead it executes as an MUUO.
s8 Codes 247 and 257, although not assigned as specific instructions, are nonetheless not regarded as “unassigned” codes. They execute as no-ops unless implemented by special hardware.
User Operations 2-127
The system instructions discussed in Chapters 3 and 5 for the other processors are also IO instructions. System in- structions for the KS10 are not IO, but for consistency and convenience they are subject to the same restriction as IO instructions (determination of their legality is done by the same microcode test). This restriction will not be mentioned in the instruction descriptions, as it applies to all instruc- tions from this point on.
As in all instructions the processor does an effective address calcula- tion, but for the IO instructions it ignores the result and recomputes an effective IO address beginning with the I, X an.d Y parts of the instruction word. The IO address specifies an IO register in some Unibus device or in the console or memory controller, and for convenience we shall refer to this effective IO address also as E. An IO address is analogous to an extended virtual address in that it has a fundamental length of thirty bits, but n of its bits are implemented in a given processor. In a KS10 IO addr &
t all ss the right eighteen bits are the register address, and the left twelve are the controller number, of which only four bits are implemented. An IO address thus has this format,
00000 REGISTER ADDRESS
0 13 14 17 18 35
where C is the controller number and bits O-13 must be zero. Of the sixteen possible controller numbers only three are used at present: 0 addresses the console and the memory controller; 1 addresses Unibus adapter 1; 3 ad- dresses Unibus adapter 3. Presently allowed IO addresses are these, and no others can be used.
Controller Register Address Specifies
0 100000 Memory status
0 200000 Console (microcode only)
1 400000-777777 Adapter 1 Unibus registers
3 400000-777777 Adapter 3 Unibus registers
The IO address calculation is like an effective address calculation in which the result can be “global”, i.e. can have more than eighteen bits.
When the result is an l&bit “local” register address, it is automatically interpreted as specifying controller 0. The calculation is limited to one level of indirection or indexing or both, and any intermediate result that is used as a memory address must be local (since the KS10 is confined to section 0).
If there is no indexing or indirection, the IO address is simply Y.
If there is indexing only and the left half of XR is negative, the IO address is the local sum of Y and XR right.
If there is indexing only and XR is positive, the IO address is the global sum of Y and XR (but remember that bits O-13 must be zero).
2-128 User Operations
-
If there is indirection only, the IO address is the contents of location Y.
If there is both indexing and indirection, the IO address is the contents of the location specified by the sum of Y and XR right.
Note that an index register can supply the entire IO address, but it can also be used to supply only the controller number when Y is the register ad- dress. This latter technique is useful for employing common code for both adapters.
BSIO Bit Set IO
714 A 1 x Y
0 a9 12 13 14 17 18 35
In the word read from IO register E, set bits corresponding to 1s in AC, and write the result back in register E.
BCIO Bit Clear IO
715 A I x Y
0 89 12 13 14 17 18 3s
In the word read from IO register E, clear bits corresponding to 1s in AC, and write the result back in register E.
RDIO Read IO
712 A I x
0 89 12 13 14 17 18
Read the contents of IO register E into AC.
Y
3s
WRIO Write IO
713 A I x
0 a9 12 13 14 17 18
Write the contents of AC into IO register E.
Y
3s
User Operations 2-129
TIOE Test IO Equal
710 A I x Y
0 89 121314 17 18
If all bits of IO register E corresponding instruction in sequence.
TION Test IO Not Equal
35
to 1s in AC are zero, skip the next
711 A I x Y
0 89 12 13 14 17 18 35
If not all bits of IO register E corresponding to 1s in AC are zero, skip the next instruction in sequence.
BSIOB Bit Set IO Byte
L
724 A I X Y 10 89 12 13 14 17 18 35
In the byte read from IO register E, clear bits corresponding to 1s in AC bits 28-35, and write the result back in register E.
BCIOB Bit Clear IO Byte
725 A I X Y
0 89 12 13 14 17 18 35
In the byte read from IO register E, clear bits corresponding to 1s in AC bits 28-35, and write the result back in register E.
RDIOB Read IO Byte
722 A I X Y
0 89 12 13 14 17 18 35
Read the contents of IO register E into AC bits 28-35. Clear AC bits O-27.
2-130 User Operations
‘Y
WRIOB Write IO Byte
723 A 1 x Y
0 a9 12 13 14 17 18
Write the contents of AC bits 28-35 into IO register E.
35
TIOEB Test IO Equal, Byte
720 A I XI Y
0 89 12 13 14 17 18 35
If all bits of IO register E corresponding to 1s in AC bits 28-35 are zero, skip the next instruction in sequence.
TIONB Test IO Not Equal, Byte
721 A I x Y
0 89 12 13 14 17 18 35
If not all bits of IO register E corresponding to 1s in AC bits 28-35 are zero, skip the next instruction in sequence.
Unibus devices generally have data registers and control/status regis- ters. Frequently a single IO address specifies two registers, one for reading and one for writing. A control register and a status register in a device usually have the same address and also have bits in common, i.e. informa- tion loaded into some of the control bits can be read as status. Ordinarily a device is set up by loading or adjusting individual bits of its control regis- ter. Data can then be read or written, and the state of the device can be determined by reading status or testing individual status bits. Complete information about the characteristics of each device is given in the device documentation.
Giving an IO address for a register that does not exist produces a page fail trap (664.3, 4.4).