t?0222J
REGISTERSm}
AOOERFigure 2-8. Data Flow Between Main Memory and Arithmetic Unit CONTROL UNIT
The control unit is the hub of central processor activities (see Figure 2-9). Its major function is to select, interpret, and execute all of the instructions in the stored program. In carrying out these instructions, the control unit coordinates the various activities of receiving data from input devices, transferring data within the central processor, and transferringproc-essed data to the output units. The main memory addresses used by the control unit in perform-ing these tasks are stored in the registers of the control memory.
Figure 2-9. Control Unit Activities
1 When floating point is installed in the 4201, the adder and operand storage registers are exten-ded to a 6-character width in order to handle floating point operands.
2-11 #2-139
SECTION II. THE CENTRAL PROCESSOR
INPUT /OUTPUT TRAFFIC CONTROL
The input/output traffic control is, as its name implies, the unit which regulates the flow (or "traffic") of data transferred during input/output actiVities. It works in. conjunction with the central processor control unit to allocate central processor time to input/output operations and to identify the peripheral controls which are to use that time to transfer data (see-Figure 2-10).
The I/O traffic control enables from 3 (Model 200 minimum) to
i6
(Model 4200 maximum) simultaneou:s input/output operations to occur concurrently with the internal computations of the processor. In processors other than the 4201, this simultaneity is achieved by the traffic con-trol's allocation of consecutive memory cycles to either peripheral controls or the cent,ralprocessor. In the Type 4201 processor, such allocation is not normally necessary, as independent cycling of memory blocks allows absolute simultaneity between memory accesses for I/O and computing operations (see page 2- 4). Only when I/O and computing operations attempt to gain access to the same memory block simultaneously does -the 4201 allocate memory cycles between the two types of operations.
INPUT DEVICE
Figure 2-10. Input/Output Traffic Control Activities
MEMORY CYCLE DISTRIBUTION
Every peripheral data transfer involves some factor which prevents the device being used from transferring data at a rate comparable to that of the central processor. Usually this factor is mechanical - moving a card through the read station or a magnetic tape or disk past the read/
write head - although in data communication it is the bit rate of the communication line. There-fore, a peripheral device requires access to the central processor to transfer information to or from the main memory during only a fraction of the time that the operation is proceeding. The
periods in which the central processor is actually interrupted for data transfer are spaced over the duration of the peripheral operation (see Figure 2-11).
L-..-_ _ _ _ ....L-CENTRAL PROCESSOR TIME REQUIRED FOR DATA TRANSFER --L _ _ _ _ _ -'--_ _ _ _ - . . I
Figure 2-11. Data Transfer Intervals During One Peripheral Operation
When a peripheral operation is in progress but is not using main memory (the gray areas in Figure 2-11), another peripheral control may gain access to the. main memory. This second memory acces s can in turn give way to a third acces s by another control before the original operation requires access to the memory again, etc. In other words, peripheral operations can occur simultaneously with one another. The periods of time in which peripheral controls do not require main memory access to transfer data are given to the central processor for its internal activities. It is the function of the I/O traffic control to direct the sharing of main memory cycles by the various peripheral devices and the central processor.
It was indicated on page 1-18 that in order for an I/O operation to proceed, the prog'rammer must specify a read/write channel in the initiating peripheral instruction. This read/write channel completes the path between main memory and the control for the peripheral device being addressed.
Input/output sectors (see page 1-22}consist of unit power loads, address assignments, and read/
write channels. Type 1251 and2201 processors may be equipped with two I/O sectors. Where this is the case, the read/write channel as signed to an operation must come from the sector to which the device being addressed is connected. Normally, this rule also applies to the 4201, which always has at least two sectors, but in that processor it is also possible to reassign RWC's outside of their "home" sectors by means of "sector escape codes" (see below).
The rate at which each peripheral control must transfer data over a programmer-assigned read/write channel(s) depends on the mechanical characteristics of the device connected to the control. Thus, the transfer intervals shown in Figure 2-11 are spaced according to the device being used. For instance, the transfer rate for the disk pack drive is considerably faster than that for the card punch; therefore, the disk pack drive will require access to the main memory more frequently than the card punch. The I/O traffic control monitors and honors the requests for access to the main memory. In processors other than the 4201, it decides how each memory cycle should be used - by a read/write channel or by the processor - as shown in Figure 2-13.
2-13 #2-139
SECTION II. THE CENTRAL PROCESSOR
The traffic control offers consecutive ITleITlory cycles to read/write channels, one ITleITlory cycle per channel. If there is a deITland on a particular channel when the cycle is offered, the channel is granted acces s to the ITlain ITleITlory for one cycle. During this cycle a single charac-ter is transferred to or froITl meITlory. 1£ the channel does not require the ITleITlory cycle, the cycle is given to the central processor for internal data processing.
In the Type 4201 processor, if an I/O operation requires access to the saITle ITleITlory block as the central processor, the I/O operation is given priority and the central processor stalls for one ITleITlory cycle. No interference (stall) occurs if the I/O operation and the central processor are accessing different ITleITlory blocks (i. e., ITleITlory accesses are siITlultaneous).
NOTE: In the Type 4201 processor, although a four-character word is ITloved in one ITleITlory cycle during internal processor operations, a single six-bit character is ITloved during input/output operations.
GIVE THE CYCLE TO THE PROCESSOR FOR MAIN MEMORY ACCESS
PROCEED TO NEXT CYCLE
GIVE THE PRESENT YES MEMORY: CYCLE TO
THE RWC FOR DATA TRANSFER
Figure 2 -12. Logical Decision PerforITled by Input/ Output Traffic Control The cyclic offering of ITlemory cycle s to read/write channels is shown in Figure 2 -13. 1£
the cha~nel being offered a ITlemory cycle is an optional channel (noted by an asterisk) that is not present in the user's systeITl, the cycle is given unconditionally to the central processor. 1 Note that every fourth Model 1200 cycle is also given unconditionally to the processor. Note further that ITlost channels available with the Models 200,1200, 1250, and2200 are offered main meITlory acces s once every six ITlicroseconds. Input/output speeds up to 167, 000 characters per second can be 1 There is one exception to thi s statement: if a Model 200 doe s not include RWC I' (Feature 016),
the cycle is offered to RWC 1.
PROGRESSION OF TIME (IN MICROSECONDS)
MODEL 200 MEMORY CYCLES:
RWC'S:
MODEL 1200 MEMORY CYCLES:
RWC'S:
MODEL 1250 MEMORY CYCLES:
SECTOR 1 RWC'S:
SECTOR 2 RWC'S:
MODEL 2200 MEMORY CYCLES:
SECTOR f RWC'S:
SECTOR 2 RWC'S:
MODEL 4200 MEMORY CYCLES:
SECTOR I RWC'S:
SECTOR 2 RWC'S:
SECTOR 3 RWC'S:
(*)cHANNEL AVAILABLE AS AN OPTIONAL FEATURE.
Figure 2-13. Sym.bolic Representation of Input/Output Traffic Control l
1This figure is not applicable to 4201 operations em.ploying channel transfer rates higher than the minimum.
2 -15 #2-139
SECTION II._ THE CENTRAL PROCESSOR
maintained by accef:)sing memory at these intervals. In processors other than 4201, transfer rates higher than those attainable with a single read/write channel can be achieved by interlocking two or more read/write channels, as described below.
Rather than interlocking RWC's, the Model 4200 traffic control offers variable numbers of memory cycles per unit of time to each read/ write channel, depending upon the read/write channel as signrnent code used in the instruction which initiates the operation. From one to six cycles are offered to a read/ write channel every 12 microseconds, giving channel data transfer capacities ranging from 83, 300 to 500, 000 characters per second. Effectively, then, the 4201 incorporates variable -speed read/write channels.
PRIMARY AND AUXILIARY READ/WRITE CHANNELS
RWC1', RWC2', RWC3', RWC4', RWC5', RWC6', RWC8', and RWC9' are called auxiliary read/ write channels becaus e of the manner in which they are granted acces s to the main memory by the traffic control. For instance, the Model 200 traffic control offers one cycle to RWC1, the next cycle to RWC2, the next cycle to RWC3, the next cycle to RWCl " the next cycle to RWC2, the next cycle to RWC3, the next cycle to RWC1, etc. In other words, memory cycle allocation alternates between a primary channel and its auxiliary channel.
Read/write channels not accompanied by auxiliary channels (e. g., RWC's 2 and 3 in the Model 200) are each guaranteed access to the main memory every six microseconds (giving a transfer rate of 167,000 characters per second), as shown in Figure 2-13. Primary channels and auxiliary channels are each granted access every 12 microseconds, because access is alternated between the two, thus providing a transfer rate of 83, 300 characters per second.
INTERLOCKING READ/WRITE CHANNELS
As indicated above, in order to achieve data transfer rates higher than those attainable with a single read/write channel, it is necessary to interlock two or more read/write channels in proces sors other than the 4201. In this manner, data transfer rates from 167, 000 to 500, 000 characters per second are possible. The same instruction which initiates the data transfer op-eration specifies whether or not channels are to be interlocked. When this procedure is used, all of the cycles normally offered to the interlocked channels are made available to the single data transfer operation. The transfer rate thus provided is equal to the sum of the rates attainable individually with the interlocked channels. When the operation is completed, memory cycle
allocation returns to normal and channels are again offered cycles at the normal intervals.
Programming procedures for channel interlocking are described beginning on page 8-110.
MODEL 4200 VARIABLE-SPEED READ/WRITE CHANNELS
As indicated above, the 4201 is equipped with variable-speed RWC's. No more than two
RWC's (a primary and the corresponding auxiliary) are ever made busy by a single RWC assign-ment. However, a single RWC assignment can still command a data transfer capacity of up to 500,000 characters per second. The most important advantage of this arrangement is that the RWC's not made busy by a high;...speed transfer are available for use in other operations. For example, in order to handle a 250, OOO-character-per-second I/O transfer, other processors would require the interlocking of several channels. In the 4200, only one primary channel will
Table 2 -4. Sununary of Central Processor Characteristics
PROCESSING UNIT
Variable. Typical configuration: op code, two address.es, and variant character.
Two-, three-, and four-character addressing. Three- and four-character addresses can specify indexed and indirect addressing.
VARIABLE FIELD LENGTH
Inforll1ation is stored in the ll1ain mell10ry in groups of characters, which are called fields.
A field is, by definition, any group of characters that is treated as a unit. Series 200 cOll1puters perll1it fields of any length, froll1 one character up to the ll1axill1um nUll1ber of character s in the ll1ell1ory. This ll1eans that an instruction or data field occupies only that nUll1ber of core storage locations actually needed.
The use of variable-length fields requires that there be a ll1ethod of indicating the actual lengths of instruction fields and data fields. This requirell1ent is fulfilled by the word-ll1ark bit
ll1entioned in Section 2. The word-ll1ark bit perforll1s the following functions:
1. It terll1inates the retrieval of an instruction.
2. It terll1inates the execution of an instruction.
3. It defines the size of a data field.
Throughout this ll1anual, the presence of a word ll1ark will be indicated by a circle around the character with which it is associated. The following points should be noted regarding the use of word marks:
1
1. Word ll1arks can be set and cleared by prograll1ll1ed instructions.
2. Word ll1arks are set by the sall1e routine that loads a prograll1 and data into the ll1ain ll1ell1ory. Usually, word-ll1ark assignll1ents rell1ain unchanged throughout the execution of a prograll1.
3. An instruction is terll1inated by a word ll1ark in the storage position ill1ll1ediately following its last (rightll1ost) character.
4. A data field is terll1inated by a word ll1ark associated with its high-order (leftll1ost) character. 1
The footnote on page 3-4 describes an exception.
3-1