Fault location in cellular arrays *

by K. J. THURBER

Honeywell Systems and Research Center St. Paul, Minnesota

INTRODUCTION

Testing of complex integrated cellular logic circuits fabricated using LSI techniques has become a source of concern to users and manufacturers. Since an economi-cally feasible solution to testing problems is not visible for the complex arrays contemplated for the near future, manufacturers have acknowledged the seriousness of the problem. Currently some observers believe that LSI cannot be tested because general procedures for testing and diagnosing digital circuits are applicable to small networks of approximately 30 gates, while cellular arrays are contemplated as containing hundreds or thousands of gates on one chip. However, if arrays are constrained to be in a cellular form, then testing problems can be simplified and test schedules can be produced which use the interconnection structure of cellular arrays.

In some cases the iterative intercormection structure of cellular arrays enables derivation of test schedules that exhibit an iterative nature, thus reducing the complexity of the testing problem in comparison with testing problems encountered in testing a noniterative structure containing an equal number of gates. It has been shown that the structure of single-rail cascades can be used to great advantage in the derivation of test algorithms for cascades ⁶ and that this testing can be accomplished from the edge of the cascade. These results are extendable to a large class of arrays. However,

* The author was formerly with the Electrical Engineering Department, Montana State University, Bozeman, Montana.

This work has been supported by a National Science Foundation Grant, No. GJ-158, a National Defense Education Act Title IV Fellowship, No. 67-06596, and an Air Force Cambridge Research

Labora tories Contract, No. F19628-67 -C-0293.

Kautz1 •2 has shown that cellular arrays exist which cannot be tested from their edge terminals.

Problem definition

The iterative interconnection structure of cellular arrays allows decomposition of testing problems for LSI cellular arrays into several subproblems. One sub-problem is the testing of single-rail cascades, such as the one shown in Figure 1. These cascades can be used in the production of more-complex cellular arrays, and tech-niques can be derived such that if a single-rail cascade can be tested then certain complex arrays can be tested.

Examination of problems encountered during solution of the problem of testing single-rail cascades using only input and output terminals of cascades produces methods that can be used to test more-complex arrays.

Specifieally, the solution of problems involved in testing single-rail cascades lends insight to methods useful in testing cellular arrays from their edge terminals by computers using an average of only two or three tests per cell contained in the array.

Figure 2 indicates the construction of an important class of cellular arrays. An example of an important class of arrays that has this interconnection structure is a cutpoint array.4 This array consists of collector rows and vertical cascades. Busses extend across all collector rows and distribute every variable across the vertical cas-cades. This construction reduces the testing of this array to the testing of a single-rail cascade, since each collector row can be tested as a single-rail cascade (under the added assumption that· both a 0 and a 1 can be placed on the input to each buss that extends across the collector rows) and each vertical cascade can be tested as a single-rail cascade. Output values of vertical 81

82 Fall Joint Computer Conference, 1969

Figure I-Interconnection structure of cascade"!

I I

c[

---dxtKhcb---cb--

_{I I I I ; I} ^f[

I I I I I

I I I I

----.,.fm _1

_m

f

Figure 2-Construction of a te~table cellula,r array

cascades are measured at the' bottom of the array whereas collector row output values are measured on the right-hand side of the array; Admittedly, it would be desirable to test all collector: rows (and all vertical cascades) simultaneously; howe\~er, to accomplish this, a restriction on the array struct&re must be made that restricts the class of testable arr~ys until the procedure becomes practically useless. '

Practical considerations

Consideration of testing problems produced by LSI chips may help develop test algorithms that could be used to test today's complex printed circuit boards.

However, complex cellular arrays in practice will be more difficult to test than printed circuit boards.

Consider that not only must exact error locations be indicated, but that a decision must be made based on the number of errors and their l~cations as to what can

be done with imperfect arrays. Are imperfeet arrays discarded or can they be salvaged in some manner?

~/finnick5 and Spandorfer⁸ have suggested that extra vertical cascades and collector rows be installed at predetermined intervals in arrays, such as in Figure 2.

If a vertical cascade or collector row has an error, then the extra cascade or row could be used to produce the correct function.

Before any test procedures can be established, an error or circuit failure criterion must be established which allows definition of possib:e error types that may appear in LSI construction. In a later section an expanded allowable set of errors for certain types of cellular arrays will be presented.

Placing an accessible test pad on an interconnection between cells reduces the effective area usable for the cells. For this reason attempts should be made to accomplish all testing and location of faulty eeils from the terminals of the array without any test p,ads being included in the array.

A test schedule could verify the complete truth table, transfer function, or state table for any given device;

however, this procedure would require too much time and would add greatly to the expense of the array.

Instead of a complete verification procedure, another Rolution could be to test certain input conditions on a probabalistic or expeeted utilization basis; however, this method is still very unsatisfactory. A feasible approach is to decide on a dominant failure mode from which a set of allowable errors can be derived for each cell type used in arrays under consideration. With this knowledge manufacturers could construct arrays using certain interconnection structures and could design cells with redundant properties. This would cause an increase in the probability that, if a failure occurs which is one of the dominant failure types, the cell error that oceurs is a cell error that is contained in the set of allowable errors.

Generation of tests and test equipment

Redundant design, failure modes, allowable errors, and required confidence level contribute to the deter-mination of the number of tests required; however, the array's structure can almost determine the number of tests independently of these factors. Test schedules are constructed to verify whether each cell is producing its specified function. This method of testing was chosen in preference to verifying an array's truth table because the number of tests needed is generally much less than m(2n+1) , where m functions of n

+

1 variables are produced. Under certain assumptions, choosing test

schedules capable of accomplishing the task of locating every error in arrays such as shown in Figure 2 is plausible (see Theorem 1), and these test schedules can be programmed for testing using digital computers.

Because of their iterative structures, cellular arrays simplify problems encountered in the detection and location of faults.

Since test schedules can be programmed for single-rail cascades, computers will be able to test many types of arrays with very minor software input changes. In particular, for the single-rail cascade under the assump-tions of Theorem 1, a general fault detection program could be written. To test a cascade the only needed input information would be the cell types and their location in the cascade. With this information the general program is able to test all cascades of one type. When the type of cascade changes, this information can be given the computer as input data and all cascades of the new type can then be tested. Because of the structural interconnection of arrays shown in Figure 2, no repro-gramming of the computer is needed when a new type of array appears.

Assumptions and definitions

Figure 1 illustrates the interconnection structure of a Maitra cascade.³ Every cell in the cascade is a two-input, one output cell. It is assumed that the Boolean variables applied to the cascade are numbered as illustrated on the cascade shown in Figure 1. All testing of the cascade is accomplished using only the input leads and the output lead of each cascade (and of arrays). The ability to measure the functional value produced by a cell by means of probing a buss connecting two adjacent cells js not assumed. To minimize the "uncertainties" (the functional values between cells cannot. be measured and the location of the error is unknown; therefore, the functional values between cells are uncertain) involved in testing cascades, it is assumed that cell n is tested first (see Figure 1), then cell n-l, etc. If an error occurs in cell n-j, its propagation may be stopped by one of cells n-1, n-2, ... , n-j

+

1. Once cell n is tested, it may be set such that it transmits the output of cell n-1 to the output terminal of the cascade. In this manner (under certain error assumptions) the cells may be tested in the following order until error location results: n, n-1, ... , 1.

The number of tests needed to test a cellular cascade is

O(n)

*,

where n is the number of cells in the cascade.

I t is assumed that only one error (faulty cell) may appear in a cascade. Also, the interconnections between cells do not fail, the error is time independent; i.e.,

* See Definition 6.

Fault Location in Cellular Arrays 83

if cell m is in error at time tl, then cell m is still in error at t2

>

tl and the error type in cell m has not changed.

Further, the input and output leads of the cascade do not fail.

I t is assumed that the 12 allowable cell functions for a Maitra cascade are fI, f2, f3, f4, f5, f6,

17,

fs, f9, flO, fn, f13, and f14. (See Definition 1 for an explanation of the notation Ii.) Seven allowable errors are assumed for each cell;

these are

hb

(s-a-l; stuck-at-one), fo (s-a-O; stuck-at-zero), fl5-p (complementation where p is the cell function), f12 (the input X), f3 (the complement of the input X),

flO

(the input V), and f5 (the complement of the input V). These seven errors consist of the two failure types (s-a-O and s-a-l) usually assumed by most fault diagnosticians augmented by f15-p, h2,

fa,

fIr'>

and fs. [Note that flO and i5 have different allowable error sets; i.e., Ehu = (fr,

i15,

f5, f12, f3) and Ef5 (fr, f15, flO, f3,

i12).J

Definition 1. The cell functions are numbered as follows:

Xi Y

i-I

fo fl

h

f3 f4 f5 f6

17

/s

/9 flO

/n

!I2 !I3

f14

/15

0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Definiton 2. An error occurs in a cell whenever the cell produces a function that is not the same as the function specified for that cell.

Definition 3. G = (ft, i2, 14, fs, f6,

17,

fa, jg,

ho,

/n,

h3,

!t4).

Definition 4. I p denotes (1, 2, 3, 4, ... p).

Definition 5. The error function E is a mapping from G x In to G, where EUh j) =

A

denotes that cell j was theoretically to produce fi€,G but instead it produced AeG. Clearly, E(jj, j) = fi indicates that cell j does not have an error occurring in it.

Definition 6. X* means either X or X', but not both.

Definition 7. O(n) means the same order of mag-nitude as n.

11 necessary and sufficient condition for fault location in cascades

Location of a single fault in a cascade is considered in this section. A necessary and sufficient condition for location of a single fault in a cascade is proven. The

84 Fall Joint Computer Conference, 1969 proof of Theorem 1 can be utilized to obtain an algo-rithm to loca,te faults in a cellular cascade or array.

Theorem 1. Given a cascade with ⁿ cells, then the error

Proof:

can be located if a,nd only if for every iEln - (1)

(1) E(fl4, i) ~ fIi)? f12 (2) E(fll, i) ~ f10i

h

(3) E(fs, i) ~ fo,

112

(4) E(h, i) ~ fo,

f3,

(5) E(fa, i) ~ f9, J12' f3 (6) E(f9, i) ~ f6, ~12' f3 (7) E(f13, i) ~ f12; flo (8) E(h, i) ~ f3,!t6 (9) E(f4, i) ~ fo, f12 (10) E(fl, i) ~ fo, f3 (11) E(flO, i) ~ fo, f15, f6 (12) E(j5, i) ~ f10,fl),!I5

The proof is an inquction proof. Clearly, the theorem is truJ for the case n = 1.

Assume that the ~heorem is true for a positive integer k and consider a cascade with k

+

1 cells. Given the cell function for cell k

+

1, if it can be shown that the error can be located in cell k

+

1 if and only if assumptions (1) through (12) are

Figure 3-Test decision map for fu

Figure 4-Test decision map for f11

Figure 5-Test decision map for fs

Figure 6-Test decision map for f2

Figure 7-Test decision map for f8

valid for cell k

+

1, then the proof is complete.

Assume conditions (1) through (12).

This part of the proof is now completed in Figures 3 through 14. Note that if Co, G1, " ' , G i are used to set Yi = C at time tI, then if Y ⁱ = C is wanted at time ~ if Go, G1, " ' , Ci are utilized again, Yⁱ is the same value as it was at it; however all that can be said about Y i is that it is either C or C', but not both. This fact is used in the proof of this theorem. In the figures with the circled function number it may be necessary to add one more test to

deter-Figure 8-Test decision map for f9

Figure 9-Test decision map for f1a

Figure lO-Test decision map for f7

Figure ll-Test decision map for f4

Fault Location in Cellular Arrays 85

Figure 12-Test decision map for f1

Figure 13-Test decision map for flo

Figure 14-Test decision map for fr;

mine whether the cell is in error or is receiving the complemented sequence.

The proof of the other half of the theorem will be by contradiction. Assume that the error can be located, but that the restlictioIlS (1) through (12) are not needed. Then it can be verified that the following pairs of conditions give the same output at the cascade's t~rminal. Since the two conditions give the same outputs, the error cannot be located, which is a con··

tradiction of the assumption; therefore,

86 Fall Joint Computer Conference, 1969

the assumption that the restrictions are not needed iA incorrect and the proof is completed. After (1) an abbreviated nota-tion is used. Note: Using the Test Decision lVlaps and the contradiction part of this proof one can actually determine the values of Y i-I.

(1) Yk = 1, 1, 1 and E(f14, ^k

+

^{1) =} f14 are equivalent to Yk = 0, 1,

°

^and

E (f14, . k

+

¹⁾ = fl5 at the cascade's output terminal.

Y^k = 0,0,

°

^{and E(f14, k}

⁺

^{1) = f14}

are equivalent to Yk = 0, 1,

°

^and

E(f14, k

+

¹⁾⁼

it2

at the cascade's output terminal.

(2) Yk = 0, 0,

°

and E(fll, k

+

^{1) =} fn;

Yk = 0, 0, 1 and E(fn, k

+

1) = fa.

Yk = 1, 1, 1 and E(fn, k

+

1) = fn;

Y k = 0,0,1 and E (fn, k

+

1) = fIr,.

(3) Yk = 1, 1, 1 and E(fs, k

+

^{1) = fs;}

Yk = 1,0, 1 an.;! E(fs, k

+

1) = !t2.

Yk

=

0, 0,

°

^{~nd E(fs, k}

⁺

^{1) = fs;}

Yk

=

1, 0, 1 and E(fs, k

+

1)

=

fo.

(4) Yk = 1, 1, 1 and E(f2, k

+

1) = f2;

Yk = 0, 1, 1 and E(f2, k

+

1) = fa.

Yk = 0, 0,

°

^{and E(f2, k}

⁺

^{1) = f2;}

Yk = 0, 1, 1 and E(f2, k

+

1) = fo.

(5) Yk = 1, 1, 1 and E(f6, k

+

1) = f6;

Yk = 0, 1,

°

^{and E(f6, k}

⁺

^{1) = fa.}

Y k = 0, 0,

°

^{and E(f6, k}

⁺

^{1) = f6;}

Yk = 0, 1,

°

^{and E(f6, k}

⁺

^{1) = f12.}

Yk

=

1, 0, 1 and E(fe, k

+

¹⁾

=

f6;

Yk = 0, 1, 0 and E(f6, k

+

¹⁾

=

fg.

(6) Yk

=

1, 1, 1 and E(fg, k

+

¹⁾

=

fg;

Yk = 0, 1,

°

^{and E(jg, k}

⁺

^{1) =}

^!12.

Yk = 0, 0,

°

^{and E(fg, k}

⁺

¹⁾

⁼

^fg;

Y^k = 0, 1,

°

^{and E(fo, k}

⁺

¹⁾

⁼

^fa.

Yk = 1, 0, 1 and E(fo, k

+

^{1) =} fo;

Yk = 0, 1,

°

^{and E(fg, k}

⁺

^{1) = f6'}

(7) Yk = 1, 1, 1 and E(fla, k

+

1) = f13;

Yk = 0, 1, 1 and E(jla, k

+

^{1) =} f12.

Yk = 0, 0,

°

^{and. E(fla, k}

⁺

^{1) = f13;}

Yk = 0, 1, 1 and E(fla, k

+

1) = f16.

(8) Yk = 1, 1, 1 and E(h, k

+

1) = f7;

Yk = 1, 0, 1 and E(j7, k

+

1) = fa.

Y^k = 0,0,

°

^{andE(j7, k}

⁺

^{1) = f7;}

Y^k = 1, 0, 1 anp E(J7, k

+

1) = fu).

(9) Yk = 1, 1, 1 and E(f4, k

+

1) =

h;

Yk = 0, 0, 1 and E(h, k

+

1) = fo.

Yk = 0,0,

°

and E(h, k

+

1) =

h;

Yk = 0, 0, 1 and E(j4, k

+

1) = !J.2' (10) Yk = 1, 1, 1 and E(fl, k

+

1) =

it;

Yk = 0, 1,

°

^{and E(it, k}

⁺

^{1) = fo.}

Yk = 0, 0,

°

^{and E(Jl, k}

⁺

^{1) = fl;}

Yk = 0, 1,

°

^{and E(it, k}

⁺

^{1) = fa.}

(11) Yk = 1, 1, 1 and E(flO, k

+

^{1) =}

ito;

Yk = 0, 1,

°

^{and E(ito, k}

⁺

^{1) = f15'}

Yk = 0, 0,

°

^{and E(flO,k}

⁺

^{1) = flO;}

Yk = 0, 1,

°

^{and E~!lO, k}

⁺

^{1) = 10.}

Yk = 1, 0, 1 and E(flO, ^k

+

^{1) = .flO;}

Yk = 0, 1,

°

^{and E(ito, k}

⁺

^{1) =}

^/5'

(12) Yk = 1, 1, 1 and E(f5, k

+

1) = !5;

Yk = 0, 1,

°

^{and E(f5, k}

⁺

^{1) =}

^!o.

Yk = 0, 0,

°

^{and E(Is, k}

⁺

^{1) = /5;}

Yk = 0, 1,

°

^{and E(/5) k}

⁺

^{1) = f15'}

Yk = 1, 0, 1 and E(f5, k

+

1) =

is;

Yk = 0, 1,

°

^{and E(/5, k}

⁺

^{1) =}

^ito.

If the cascade meets the assumptions of Theorem 1, then Theorem 1 can be used to determine test schedules for the location of an error in cascades. It should be noted that when cell k is tested, one obtains information about the cells k - 1, k - 2, .. " 1, and therefore a test schedule with O(n) tests will test any cascade with n cells under the allowable error set6• Clearly, if the conditions of Theorem 1 are relaxed, then fault detection (and maybe isolation) can be accomplished in the same number of tests; however, if one is only interested in fault detection, Theorem 2 is the best technique to use.

If a more complex cascade than the casca.des con-sidered here is under consideration,· then a good understanding of the method used to derive the theorems in this paper will allow one to extend the theories presented. If the cell functions fo, fa, !J.2, and f16 are allowed, then the fault techniques may be easily extended since none of these functions depend on the Y value; however, one must exercise care in the use of the theory because it is based on the ability of the tester to place theoretically both a

°

^{and a 1 on the Y}

inter-connection, and examples (trivial) in which this cannot be accomplished do exist.

Fault detection in Maitra cascades

In

this section the detection of a single ftmlt in a cascade is considered. The theory for this section is based on the observation that every n cell Maitra

cascade (as defined in this. paper) produces :;I. function

Since Xl can be made (by a suitable choice of constants~

to pass theoretically through every cell

*,

the theorem could be rewritten in terms of Xl. In terms of the complexity of the detection scheme it is seen that cascades could have a very simple detection test schedule. It should be noted that Theorem 2 can very easily be adapted to provide fault detection in cascades if it is assumed that flO is not an allowable error for any of the 12 cell functions.

Examples

This section consists of examples of the use of Theorems 1 and 2. fA denotes the measured value of f whereas fT denotes the theoretical value of f.

* Assuming the cell function for cell 1 is not flO or f_6•

Fault Location in Cellular Arrays 87

Example 1. Assume that there is no error in the cascade shown in Figure 15.

Test the cascade shown in Figure 1.5.

[(Xo

+

^Xl

+

^Xz) Xa]

EB

X4 = fT(XO, Xl, X2, Xa, X4)

!T(XO, 0, 0, 1, 0) = Xo

fA(O, 0, 0, 1,0) = fT(I, 0, 0, 1,0) = 0 implies that there is a cell i such that E(f p, i) = fo, it5, it2, or fa.

88 Fall Joint Computer Conference, 1969

xo

--1 ^t _H ^{C (3} r

⁴

f14 f14

H

^fa

^H

^f6

^~f

Figure 15-A cascade to: be tested

CONCLUSION

Techniques for fault location an~ detection in cellular arrays with an allowable error set of fo, f16, !I6-p, fa,

!I2,

f6, or flO were described in this paper. It was shown that the problem of testing an array could be reduced to the problem of testing a cascade. The solutions presented are particularly attractive because of their simplicity.

To locate an error, ^O(n) tests are needed for an ⁿ cell cascade. Detection of an error requires only two tests if the allowable error set is reduced by one error (flO).

A necessary and sufficient conclition for single-error location was given. If the restrictions of this condition are relaxed, then an isolation theorem such as given by Thurber ^6,7 can be derived; however, this isolation condition will be more complex t~an the theorem given by Thurber ^6,7. A criterion that enables detection of a single error in only two tests was! derived.

Although the theories presenited were derived for regular arrays of logic, they have ,potentially wide areas of application. A good understanding of the philosophies presented here will allow the extension of the results to cascades of m input n output cellf';. Also, some irregular arrays may be tested using this ,theory if they can be decomposed into sections composed of some form of a cascaded structure (or sections composed of structures

closely resembling a cascaded structure).

ACKNOWLEDGMENT

The author wishes to thank R. C. Minnick for his help in the preparation of this paper.

REFERENCES

1 W H KAUTZ

Testing for faults in combinationa,l cellular logic armys 1967 Switching and Automata Theory Symposium 2 W H KAUTZ

Diagnosis and testing oj cellular arrays, properties of cellular arrays jor logic and storage

SRI Project 5876 Scientific Rpt No 3 July 1967 119-145 3 K K MAITRA

Cascaded switching networks oj two-input flexible cells IRE Trans on Electronic Computers Vol EC-ll April 1962 136-143

4 R C MINNICK Cutpoint cellular logic

IEEE Trans on Electronic Computers Vol EC-13 Dec 1964 685-698

5 R C MINNICK

A survey of microcellular research

Journal Association for Computing Machinery Vol 14 April 1967 203-241

6 K J THURBER

Fault location in cellular arrays

PhD dissertation Montana State Univ June 1969 7 K J THURBER

Fault location in cellular cascades Submitted to IEEE Trans on Computers 8 L M SPANDORFER J V MURPHY

Synthesis of logic .functions on an array of integrated circuits Scientific Rpt ~o 1 for UNIVAC Project 4645 AFCRL-63-.528 Contract AF 19(628)2907 Sperry Rand Corp UNIVAC Engineering Center Oct 1963

Im Dokument FALL JOINT COMPUTER CONFERENCE (Seite 89-97)