for LSI
by F. D. ERWIN and J. F. McKEVITT
Hughes AircraJt Company Fullerton, California
BACKGROUND
Since the advent of LSI technology, several schemes have evolved for the utilization of large arrays to their full potential. A common and straightforward approach involves the designer restricting himself to the equip-ment being designed at the moequip-ment. Faced with only a limited set of problems, it is not difficult to specify a small number of LSI array types which will efficiently complete the design. While the results are quite en-couraging for specific cases,! the drawbacks of any mass adoption of these techniques are obvious. This, the so-called "custom approach," would require the semi-conductor manufacturer to be responsive to each cus-tomer with numerous low-output production runs of highly specialized devices. The per-unit cost to the user, for his own efforts as well as those of the manu-facturer, would be quite high due to the inability to spread initial costs over many devices. In addition, the complexity of lOO-gate-plus arrays is such that it is difficult to substitute one for another (with efficient results). This would severely limit the· off-the-shelf capabilities of both user and manufacturer.
An obvious solution to these problems is the intrq-duction of a small set of standard LSI chips. Semi-conductor suppliers, making tentative advances into LSI product marketing, have already proposed such devices as adders, counters, and shift registers. How-ever, this does not represent the solution to the general problem. A design heavily committed to the use of these devices must fall back on MSI or standard I C for the large remainder of the circuitry. The reason is that adders, counters, registers and other orderly,
well-69
defined areas represent the regions of the system with the highest gate-to-pin ratios. After these portions are lifted out of the system, the remainder is characterized by very low gate-to-pin ratios (notably control and data routing functions). Unable to satisfy the LSI design criteria of high gate-to-pin ratios any longer, the designer must look to more standard components.
Unfortunately, any proposed solution to the LSI partitioning problem which lacks a total system ap-proach tends to drift towards this pitfall.
Researchers striving towards partitioning for total or near-total LSI implementation tend to diverge along one of two conceptual paths; bit-slicing and functional partitioning. To illustrate the difference, consider the data portion of the computer. In functional partitioning one may specify an adder as one LSI ar-ray, registers as another, a shift register as a third, and so forth. On the other hand, in bit-slicing one would design an LSI array consisting of a combined one- or two-bit adder, registers, shift registers, etc., then build up his system from this chip type according to the de-sired word length.
The bit-slice approach has resulted in some notable advantages, particularly the ability to achieve very high gate-to-pin ratios and implement systems using a small number of different array types.1,2 However, bit-sliced mod~les have the basic flaw of being system-dependent, a drawback described by Pariser in an early paper.3 This means that behind such bit-slicing approaches there lie systems, real or implied, for which the resulting arrays are most efficient. An attempt to apply the arrays to a significantly different system results in a poor design. Considering the types of
bit-70 Fall Joint Computer Conference, 1969
.~---~---~---slice devices being proposed, inefficiencies would most often be manifest in the design of a simple device in which the majority .of the gates qf the array intended to accomplish complex functions ~re wasted. Although this may be acceptable in some: situations, it is un-likely that it would satisfy the strict requirements of size, weight, power, and reliability imposed by aero-space and military systems.
It is the contention of this p~per that a judicjous partitioning of digital systems in general, divorced from bias towards any particular system, results in a set of LSI devices that can entirely implement many different computer systems of varying functional com-plexities and word lengths.
The resulting group of array~, referred to as a
"character set" and each one indiyidually as a different
"character", is sufficiently small ib. number (10), with func-tionally-partitioned nor bit-sliced, it is biased towards functional partitioning to give it the versatility to efficiently implement both comple* and simple digital devices. As an approach, functio~al partitioning has a detailed and successful backgtound.3 ,4 Bit-slicing consideratoins give the character set its ability to implement systems of varying word lengths.
In addition to providing the u~er with a standard
Introduction to the character set
A universal conclusion among LSI researchers is that control functions are more difficult to modularize than functions related to data :operations. Micro-memory control technique was chdsen as the solution for LSI implementation for several reasons. A micro-memory, meaning here a read-only Bolid-state memory with its sequencer and instruction register, is easily partitioned into the large modules! necessary for LSI implementation. Control fUllctions in this form are
then amenable to reproduction in large quantities of identical units. Also,design with control centered in one level of micro memory is more orderly and straightforward.
The micro memory has been provided with a rela-tively sophisticated microprogram instruction reper-toire. This means that the microprogram contains the essence of the machine's major mathematical func-tions, such as multiply and complex sequencing. This is desirable since it represents an efficient use of hard-ware for these purposes and also reduces the number of different array types necessary. Also, a versatile rep-ertoire leaves the designer free to make units which operate as simply or as complexly as desired. The
~egree of flexibility which this repertoire gi ves the character set is a major factor in its success. It should be stressed that the "micro operations" of the I~harac
ter set are as important a factor as its logic design. This fact, a critical one in all LSI solutions committed to micromemory control, cannot be overemphasized.
Interest in designing a character set at Hughes was concurrent with the development of an advanced com-puter system. The character set itself was developed with the ultimate objective of implementing all future Hughes digital data processing equipment with a com-mon family of LSI circuits.
The outcome of that original effort revealed that computer structures in general are frequently ordered, or at least amenable to such ordering, as shown in Figure 1.
The divisions of Figure 1 are functional. That is, regardless of the hardware characteristics, the computer philosophy is such that its functions may be identified, separated, and diagrammed as shown in the figure.
From Figure 1 came the concept of the funetional character set. With the fundamentals of LSI design in mind, logic was designed to accomplish each computer
COMPUTER
BOOLEAN LOGIC FUNCTIONS
• MINORI TRANSFER, SHIF1',
Ml
ta
M2 M INPUT /OUTPUT FUNCTIONSII
L.. _ _ ----I. _ _ _ -...J~:~~s~~~~ss
II
L... _ _ ----1. _ _ _ ...SCRATCHPAD
!
~----j.----I
g~~~'::-ER·I ~ _ _ --j. _ _ _ - I
SWITCH
I
L..-_ _ ---I. _ _ _ ~~.BITS---1
CORE MEMORY DEFINED AS AN I/O-TVPE DEVICE
Figure 2-Functional charf:l.cter set
function indicated by the picture. Each unique LSI chip type which resulted was referred to as,a different character type and given an identifying name and number. Figure 2 shows the character set which re-sulted from the logic design according to the concepts outlined in Figure 1.
The character set and repertoire have been through several improvement cycles and used in the test im-plementation of a NASA computer to be discussed later. Current plans include test design of the H4400 (a new Hughes computer) with the improved character set, implementation of the character set with high speed ~IOS circuits, and construction of one computer using the characters.
These ten LSI characters alone provide the entire hardware complement for the logic of a broad range of computers and digital equipment. No extra logic in the form of either IC, MSI, or custom LSI need be added to the characters to finish the job. An important by-product of this is that the user need never consider logic design. His tasks are reduced to selection of the necessary characters and the writing of the appropriate microprograms for them. In fact, it is possible for the character set to fit into a realistic total design automa-tion procedure as discussed later.
Description of the character set
This section describes each of the ten characters.
They are summarized below for reference.
G 1 Register storage Ll Generallogic L2 Arithmetic logic L3 Input/Output
Ml Micromemory counter M2 Micro-instruction Register
Characters-Universal Architecture for LSI 71 M.M Micro-array
PI Scratch pad memory P2 Up/Down counter P3 Switch
Characters of the same letter are logically grouped into a common unit as illustrated in Figure 3.
G 1 character
The G 1 character provides the bulk of storage for operands of the microprogram. Each character con-tains four registers of eight bits each accompanied by reading and writing selector gates. The storage element is provided with simultaneous dual reading and writing capability. The storage flip flop itself is designed for minimum read after write delay.
Eaeh of the two input busses is common to all registers and carries to the G 1 character eight lines per bus, one line from each bus for each bit of the register. Input data selection is accomplished at the memory element by a coincidence of positive infor-mation on a particular input bus and register selection for that bus by destination decoding logic within the character. The destination decoding logic is duplicated to provide for writing from the two input busses into the same character under control of two different micro-commands. As will be illustrated later, this is a key factor for the machine expandability property of the character set as it allmvs G 1 to form a data path link between individual logic units under control of up to two' different micromemories. Different registers in r,he character may be written into simultaneously.
Reading of the register is provided by dual source decoding logic which gates data to independent dual output busses. This duality provides for information from any two registers to be simultaneously placed on two output busses. The conceptual structure of the G 1 character is shown in Figure 4.
Several G 1 characters placed in parallel provide registers of more than eight bits in length.
Figure 3-Typical functional character configuration
72 Fall Joint Computer Conference, 1969 L1 character
The Ll character provides the basic logic functions selectable by microprogram. In addition input bussing is provided for nine channels (eight bits/channel).
One channel of the bus is required for each G 1, L2 or or L3 character connected to the L1 character. The logic functions provided consist of the rotates, shifts (logical), no-operation, complement., and incrementa-tion. Also associated with the L1 charac>ter is the de-coding logic for these logic operations. The type of microprogramming used with the functional character system relies heavily upon the fast and efficient manip-ulation of bits within the various operands. To this end, shifts and rotates have been: provided which exe-cute from 1 to 31 positions in a single step (as op-posed to serial operation). Incrementation is accom-plished with the use of a logic register which may also be used as a simple holding register. The L1 character is eight bits wide and contains the following logic:
1. Bussing gates 2. Decoding logic
3. Rotate, slJift, and complement logic 4. Incrementer
5. L register
6. Gating to output bus
In Figure 5 is shown a block diagram of the L1 character. Several L1 characters may be connected together to form logic operations on words longer than
r
-I
I IENCODED ENCODED
SIGNALS SIGNALS
Figure 4--G 1 character block diagram
91112-1'
L_-,
I I I
MICRO.
MEMORV CONTROL
GENERAL LOGIC I
L _ _ _ _ _ _ _ _ _ _ _ _ F~I~ .J
Figure 5-Ll character block diagram
une byte. A limit of four bytes exists in order to main-tair! consistency of definition in the rotates and shifts.
Information entering the L1 card from the various sources is bussed to form the input bus. Then it is operated upon and the resultant is bussed to the out-put bus where it leaves the character or is optionally stored in the L regist.er (",here it would thus be available at the next mirro-instruction time for use in the incre-ment operation or as an "L" source).
L2 character
The L2 character provides the major arithmetic functions used by the microprogram. The arithmetic unit provides the 2's complement sum of the con-tents of the A and B registers. Addition is performed with carry look-ahea'l byte parallel. Control signals may copditioll the adder to alternately provide either of two special results (a) a mod 2 addition instea.d of full addition or (b) an input carry to the lowest order bit for full addition (this forced carry in conj unction with a negated operand accomplishes a 2'B com-plement operand for subtraction). The L2 character consists of two holding registers for the operands of the adder, the adder itself, decoding and error logic, and bussing gates. Figure 6 dia.grams function-wise the L2 character.
A typical arithmetic operation using the L2 charac-ter might proceed as follows: (1) first operand traIlS"
ferred to· B register (from output bus), (2) second operand transferred to A register, (3) after appro,priat.e delay access result and transfer out of L2 charact.er via the input. bus. The error logic provides overflow and carry-out information.
Characters-Universal Architecture for LSI 73
r---~
I 1 1 I I I I
Figure 6-L2 character block diagram
L3 character
The L3 character provides input/output capability for the microprogram machine. For purposes here input/ output includes not only the usual peripherals but also main memory, scratch pads, real time clocks, an P -charact.ers-namely all elements of the computer not directly controlled by the micromemory. The L3 character provides iDput gating for external devices-four buffered and three non-buffered channels. The
buffered-input gatiDg may be controlled either by the microprogram or the external I/O device itself. Four I/O output channels are provided. Interrupt signal storage and int.errupt mask storage for four channels are available. Parity generation and checking along with odd/even control is provided for the four buffpre<i channels. L3 also contains the necessary register des-tination and selection logic. Figure 7 is a block diagram ofL3.
To input data, an input line is selected under micro-program control resulting in selected data entering an.E register or, in the case of a non-buffered input, entering the input bus. To output data, the micro-memory places the data in the appropriate E register and signals the corresponding I/O unit. The E registers themselves are available to the logic unit in a manner identical to the 0 registers (01) independent of their input/output functions.
Ml character
The MI character provides the micro memory address register and related functions. The ten address bits of MI allow for addressing up to 1024 micromemory words. The address is containod in the lV[lvIC (Micro
r---.,.LL..L...U. ...
I ~~+h
I I I I I I
INPUT _;...1 -++-~--+--I I
I I I I I I I I I
DESTINATION '---_~OECODE
'---ENCODED
SIGNALS ENCODED
SIGNALS
Figure 7-L3 character block diagram
INTERRUPT (mIl
Memory Counter) register and serves to address the micro memory proper. Associated with the. lVIl\IC register is a five-bit incrementer which automatically steps through 32 microprogram address states and then repeats addresses. This produces the effect of a microprogra.m riLg of 32 words in which the program will loop until the microprogram issues an unconditional transfer command. There is an S (save) register that allows for subroutine jumps. The S register saves the content of MMC upon command, keeping it available for reinsertion into MMC. Figure 8 shows the block diagram for Ml.
Branching or transferring within the microprogram is provided by two modes: unconditional transfer ~f full 10-bit width and conditional transfers of four bIt
Figure 8-M 1 character block diagram
74 Fall Joint Computer Conference, 1969 width. The Ml character carries the time base whose signal is distributed to other characters.
M2 character
The M2 character contains a micro memory word register. The register is 49 bits long providing for a full micromemory word. Forty-nine bits are divided into two 16 bit fields and a 17 bit field. The first and the second fields are instructions and the third is a constant. The second instruction is transferred into the register loca-tion of the first for execuloca-tion resulting in sequential exe-cution of the two instructions in the micromemory word: Timing is derived from the timing base on the Ml card. Figure 9 shows the block diagram of M2.
MM character
The MM character contains the i micro memory array.
The address register and word register for the array are located on Ml and M2 respectively. MM is a read-only array. The presence of an address on the input lines causes the contents of the referenced location to appear on the output lines after an appropriate delay.
The Ml\1 character consists of 256 words of 49 bits
r---
I----,
I I I
I I
MICROMEMORV ADDRESS
I I I I I
j
M'CROMEMORV : . WORD REGISTER I~--~~~~
I... tc:.:. ... .!!!;:c~
::!,d
MICROAAAAV ClO-tllS
Figure 9--M2 char<1octer block diagram
r - - - ,
I MICAOME'-WAY
WORD
Figure lO--MM character block diagram
each. Figure 10 shows the block diagram of MM.
Several MM characters may be combined to form a larger micro memory array. The maximum organization is 1024 words by 98 bits.
PI character
The PI character is a scratch pad memory of 256 bits of storage with associated address decode logic, address register and data register. The scratch pad is arranged into 16 registers of 16 bits each. Figure 11 is a block diagram of PI.
The PI character is connected to the L3 character through which its data flows. Up to 16 PI's may be connected in series to produce a total scratch pad of 256 registers. Generally the bit width will match that of the logic unit.
P2 character
The P2 character is an expandable eight-bit eounter with byte look-ahead logic. The introduction of a time signal produces a real-time binary clock. The eounter may be read in parallel and is resettable to any desired value. Zero detection is provided which may optionally interrupt the microprogram and/or the main program.
The P2 character is connected to the L3 character through which data and control pass. Figure 1~: shows the block diagram detail.
The P2 character contains control logic allowing the counter to be in a run state or stop state dep~ndent
upon microprogram control.
P3 character
The P3 character provides the capability of switching any three input channels to any three output channels.
,--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 91112-10
II 0 ~:;:::S
:ST:-,~
I
16 BITS1.:: ::RAY
-,
I
Figure ll-Pl character block dia.gram
Characters-Universal Architecture for LSI 75
---PREVIOUS
6
READ/WRITEr--- :sL _____ ,
STAGE(P"~7 N£XT STAGE (P2,
CLOCK I . I
(Ml)
I ~RUN/sTOP QUP/OOWN I
L3 L_~ _ _ _ _ _ _ ....!E~M~OC.:J
Figure 12-P2. character block diagram
L _ _ _ - '
Figure 13-P3 character block diagram
A 16-bit width is provided. This configuration allows three simplex simultaneous connections. Figure 13 shows the block diagram for the switch.
The input and output channels of P3 may be con-nected to any external interfaces which are electrically compatible. Storage is provided on the character for nine bits of control information establishing the state of the switch.
There is no restriction on the switch state; all pos-sible configurations are allowed (such as three inputs to three outputs, one input to three outputs, three
There is no restriction on the switch state; all pos-sible configurations are allowed (such as three inputs to three outputs, one input to three outputs, three