Chapter 5. MOS Random Access Memory Design
5.3 Dynamic RAM Cells
The nearly infinite input resistance of the MOSFET provides a temporary data storage node which can be used to simplify RAM cell circuitry. Using this capability, information can be stored for a finite length of time on the gate of the MOS device.
The p-n junctions which are inevitably connected to the gate regions and the accompanying junction leakage currents are small enough so that charge can be stored on the gate capacitance and gate parasitic capacitances for times of milli-seconds to tenths of milli-seconds. Of course, some electrical method must be provided for refreshing the gate prior to loss of data. It will be recalled that it was this type storage that permitted successful operation ofMOS dynamic shift registers; this type storage will also provide the means for operation of the dynamic RAM.
5.3.2 The 4-transistor Dynamic RAM Cell
As a first example of dynamic RAM cell circuitry, let us consider how a static cell such as the 6-transistor configuration previously discussed can be operated dynamically in a 4-transistor configuration, thereby realizing a reduced device count. To achieve the configuration, the load transistors of the flip-flop are operated in a clocked mode and the load transistors are simultaneously used as elements by which the cell can be accessed as shown in Fig. 5.5. The cell will thus hold informa-tion which has been set into it, when T3 and T4 are activated by clock pulse cpo When the clock voltage turns off, T3 and T4 are off and the charge on C1, resulting from the previously set condition of Tl on and T2 oft will gradually leak off through the drain junction of T2 and source junction of T4.
The cell will eventually lose its information content and therefore must be re-freshed. This can be done quite simply by turning T3 and T4 back on with a clock pulse, cpo At 70°C, the clock pulse must come on every 2 ms and stay on for a few hundred nanoseconds to restore the charge on capacitor C1 • The flip-flop, of course, remembers the state it should be in, since prior to refresh all the charge (and hence voltage) was not permitted to be lost from C1. The refresh method for this cell is, therefore, quite direct and is probably the simplest in operation of all dynamic cells which we will consider.
To utilize this 4-transistor cell in a memory array, the overhead circuitry shown in Fig. 5.6 must be employed. The cell is refreshed by the row (word) select line,
v
Vss
Fig. 5.5. A 4-transistor dynamic RAM cell.
Row
select
D,
Vss
J 1m
L~Co~lu~m~n~d~ec::o~de:.s1
---=t:=---'o
chipselect Fig. 5.6. The 4-transistor dynamic RAM cell with overhead circuitry.
which must be activated every 2 ms. The column decode and chip select complete the path to the output, and the differential current that exists on the lines is sensed for reading the state of the cell. Writing is accomplished by forcing line Dl or D2 to ground with external signal application when the cell is selected by the row select line.
Advantages of this cell are its high speed, short cycle time, and straightforward refreshing method. Disadvantages are that the writing operation is complex and the cell size is fairly large, ;:::::::15 sq mils. This form of RAM cell is popular, however, and its application in a 1,024-bit RAM configuration will be presented later in this chapter. Meanwhile, let us determine what can be done to further reduce the device count and cell size in MaS dynamic RAM cells.
5.3.3 3-transistor Dynamic RAM Cells
When discussing the dynamic operation of MaS circuits, it has been noted that charge (i.e., information) can be temporarily stored on the gates of MaS transistors.
Thus a logic 1 can be represented by sufficient charge storage to turn the device on. A logic
°
can be represented by a low charge state resulting in an off state condition for the device. This basically implies that it should be possible to make a major departure from the classical flip-flop arrangement in the design of a dynamic RAM cell. Such is the case for the 3-transistor cell shown in Fig. 5.7.5 Operation of this circuit is as follows. Transistor T2 is the information storage element where charge stored on capacitor C determines the state of T2. Transistor T3 connects T2 to data out when T3 is activated by a read select signaL Tl , when activated by a write select signal, transfers input data to the storage element T2• Tl also provides refresh of the information storage element T2 by means of a clocked refresh amplifier which is connected between the read and write lines, thereby closing theRead s e l e c t f j
~
Tl T2 T3Wdte
let
= ReadWrite select
Fig. 5.7. The 3-transistor dynamic RAM cell (3-2-2 config-uration).
loop on the memory cell (Fig. 5.8). A single refresh amplifier can, therefore, service an entire column of cells in a memory array.
A memory cell shown in Fig. 5.7 is often referred to as a 3-2-2 cell since it has 3 transistors, 2 address lines, and 2 digit lines. These descriptive numbers are important because they relate to cell size, which must be minimized. This cell is used in the type 1103 RAM.6 Cell area achieved is ;.::::6 sq mils. The separate read and write lines to the cell make it inherently fast.
Now there are other configurations of 3-transistor dynamic RAM cells. For example, the 3-1-2 configured cell shown in Fig. 5.9 has the advantage that one address line serves both read and write select functions resulting in reduced cell size. Unfortunately, a race condition develops unless read and write address pulse shapes and voltage levels are very accurately tailored. This disadvantage has hindered the adoption of this particular cell.
Another configuration, the 3-2-1 cell, is shown in Fig. 5.10. Read and write signals are presented on a common line, resulting in cell size reduction to ;.::::5 sq mils with p-channel technology. This cell is relatively easy to refresh. Since the cell forms a loop on itself (the read/write line is a common bus), the cell refreshes itself in a complementary manner and refresh amplifiers are eliminated. This cell is often referred to as an inverting cell. 7 A data control register must be provided to keep track of the refresh status, but that turns out to be a relatively simple requirement for a matrix array of cells. The 3-2-1 cell configuration thus holds promise for MOS RAM applications.
The available 3-transistor dynamic RAM cells are characterized by access times less than 300 ns, 0.1 to 0.5 m W per bit power dissipation in the active mode, and less than 10 p,W per bit dissipation in the standby mode. Silicon area required for these cells of p-channel variety is ;.::::5 to 8 sq mils.
Write
Read select
I
T3'---...
---~ Other
1---~ Cells
r---Refresh
amplifier Control Read
Fig. 5.S. The 3-transistor dynamic RAM cell with overhead circuitry.
Write
Read / write select
I
=:=c
I I I*
Read
Fig. 5.9. The 3-transistor dynamic RAM cell (3-1-2 configuration).
5.3.4 The l-transistor Dynamic RAM Cell
Read select
I
Write select Fig. 5.10. The 3-tran-sistor dynamic RAM cell (3-2-1 configuration). 7
What further reduction in component count can be made for the MOS dynamic RAM cell? Let us consider the ultimate-a 1-1-1 configuration. Such a cell features I transistor, I address line, and I digit line. Cells of this type have been successfully fabricated,8,9, 10, 11 and they take the circuit form of I transistor in series with a storage capacitor, as shown in Fig. 5.11. The transistor serves as a switch, permitting charge flow either into or out of the capacitor storage element when read or write select is activated. This cell's major problem is that of obtaining a large enough voltage swing to read information out of the cell easily. This problem arises because of the large ratio of bit-sense-line capacitance C2 to cell-storage capacitance C1. Thus, in the readout of the original voltage stored on capacitance C1, a reduction of the initial voltage across C1 will occur as indicated in Fig. 5.11. This results in a voltage sensing problem and poor noise immunity. In design, the ratio of bit-sense-line capacitance C2 to cell capacitance C1 is therefore held to a value of less than 10 to 1. To further alleviate the problem, the following design steps can be taken:
The storage capacitance of the cell can be increased, the storage capacitance of the sense lines can be decreased, or the sensitivity of the sense amplifiers can be increased.
Fig. 5.11. The I-transistor dynamic RAM cell (1-1-1 configuration).8
Read / write select
Read/write
VR=Vi
(C;~C2)The capacitance of the sense lines consists of the gate overlap capacitance of the cells plus the junction capacitance of the p-diffused read/write data bus. Without departing from standard fabrication techniques, this implies that ~I sq mil per cell is occupied by the thin-oxide MaS storage capacitor C1• The resulting large area of thin oxide required for a 4,096-bit RAM matrix contributes to yield loss. There-fore, design development is required to minimize this capacitance. Special design is also required for increase of sensitivity of the sense amplifiers.9,lo,1l In addition, readout of this particular cell is destructive; therefore, overhead circuitry is required to internally rewrite the data into the cell after it is read. This circuitry can also be used to refresh the cell at periodic intervals. A disadvantage of the I-transistor cell is the large ratio of overhead circuitry required in addition to the sense amplifiers.
These factors are balanced, however, by the advantages of the cell such as high speed (~300 ns access time), small cell size (~2 sq mils), and simple cell structure.
Note that the component spacing is not as critical in the I-transistor cell as it is in the 3-transistor cell. Adoption of the I-transistor cell thus depends upon the answer to this question which relates to manufacturing: Is the dominant factor the simple structure, or the large area of thin oxide required for the storage capacitors?
Until this question is resolved, further development efforts will continue for both the I-transistor and the 3-transistor MaS RAM cells.
5.4 PRODUCT EXAMPLES