Characteristics of the Desired Semiconductor Storage Element 25

2

Seven basic design goals must be considered when evaluating the array of semi-conductor technologies available for performing the storage function. These goals directly affect the characteristics of semiconductor storage elements. The first and foremost goal is economy consistent with the level of performance required including speed, reliability, and other factors. Economy is measured in terms of cost per bit.

The primary competition of semiconductor memory is, of course, magnetic devices such as core, plated wire, drum, and tape. To be competitive, semiconductor random access memories and fixed program memories must be in the tenths of cents per bit range. Sequentially accessed semiconductor mass memory must attain a cost goal of tens of millicents per bit. Projections indicate these economic goals will be attained by the mid-seventies. Whatever technologies are selected must be compatible with these economic estimates or must lead to further cost reductions.

A second design goal is that of low power dissipation per bit. This is important since it is desirable to constrain our overall electronic system to a physical size which is as small as possible. Resulting heat dissipation becomes a major factor working within this constraint.

A third characteristic to be attained and one which is interrelated with low power dissipation is speed performance. Achieving high-speed performance, defined in terms of bit rate, access time, or cycle time, is important because it enables data processing time within the electronic system to be kept minimal. The result is more effective use ofthe system. Fundamental limitations arise when attempting to achieve fast switching speed and low power dissipation simultaneously. In practical termi-nology, power dissipation and operating speed are related through the so-called speed/power product. The resulting numerical product is determined by the char-acteristics of the chosen device technology. Expressed in units of energy, the speed/

power product is, therefore, directly related to the efficiency with which a logic or memory function can be performed. The speed/power product concept, as it relates to the various technologies, will be considered in detail later in this chapter.

25

A fourth desirable goal to be achieved is small area per bit. The area per bit will, of course, directly affect the overall system size. Encouraging possibilities offered by semiconductor storage elements are demonstrated by a comparison of 4K bits of MOS semiconductor random access memory with 4K bits of magnetic core, Fig. 2.1. In addition, the cost per bit is directly related to the silicon area per bit required for a given semiconductor storage function. So for maximum economy, considerable design effort is expended reducing the silicon area per bit.

Nondestructive readout and nonvolatility of the memory cell can be considered simultaneously as the fifth and sixth design goals. Nondestructive readout is desir-able because, with its realization, data processing time is not wasted recirculating data back into the memory cell after the read operation. Nonvolatility is desirable because it permits the cell to maintain its memory content despite possible power-supply disruption; reprogramming after reenergizing of power supplies is, therefore, unnecessary. Magnetic memory elements suffer from destructive readout, but do offer nonvolatility; semiconductor memory cells suffer from volatility, but offer nondestructive readout.

The required reliability of the semiconductor memory element is the seventh design goaL The mean time between failures (MTBF)l of a memory system determines the repair and maintenance cost, as well as the system availability. Assessment of the system's mean time between failures requires a knowledge of the failure rates of the components which comprise the system. The approximate failure rate that could be allowed for a 1,024-bit RAM used in a 10 million bit memory system, where the repair frequency is once every month, is 0.007 percent per 1,000 hours per 1,000 bits. Although these low failure rates are presently available with existing circuits, the technology must be utilized in such a manner as to increase the reliability and the mean time between failures in order to implement even larger machines with improved reliability. Thus, particular attention must be given to semiconductor technologies such as diffusion, oxide growth, ion implantation, metalization, bonding, and packaging. This attention is essential because new semiconductor storage

II II

4K bits of core RAM

II

Each 1 K bit chip is

III

elements are continually being developed which require fabrication techniques whose resulting product reliability has not been established previously.

2.2 REVIEW OF PRESENT-DAY SEMICONDUCTOR MEMORY CIRCUITS

Since much present-day technology is directed toward using bipolar devices in semiconductor memory circuits, let us begin our analysis with these devices. The bistable flip-flop, Fig. 2.2, consisting of two cross-coupled inverters, has been the basic storage cell adopted for bipolar random access memories (RAMs) and also serves as the basis for presently available bipolar sequentially accessed memory elements (shift registers). With two stable states, the flip-flop memory cell stores information in the form of Is and as. The storage states are stable (static operation is possible) until an externally applied signal changes the situation. Enjoying high yield, the cell has good operating speed capabilities and provides a cost-effective design.

The simplicity of bipolar fixed program or read only memory (ROM) is illustrated by the representation of the memory matrix shown in Fig. 2.3. Because of its simplicity, ROM circuitry requires only small area per bit. Therefore, many more bits of ROM can be fabricated on a given size chip than is the case for RAM and sequentially accessed memory circuits.

In an effort to reduce area per bit in bipolar RAMs, emphasis has been given to circuitry which departs from a static mode of operation with classical flip-flops to that of a dynamic mode of operation featuring greatly simplified circuitry. The operational basis of this circuitry is charge storage on the capacitance of reverse-biased p-n j unctions. ² Because of leakage current, memory cells which operate on the principle of charge stored on p-n junction capacitance eventually lose their in-formation content and must be refreshed at intervals less than a few tenths of a

Rc

Fig. 2.2. The basic bistable flip-flop (bipolar technology).

~~--rl---r--1 1 0 1 0

Fig. 2.3. Representation of the basic bipolar ROM circuit.

28 Semiconductor Memory Design and Application

second. Such circuits are operated, therefore, in a dynamic mode and are referred to as dynamic memory circuits. These contrast with the static operation of flip-flop memory elements. Developmental efforts will undoubtedly continue to reduce the device count and silicon area consumed per bipolar memory cell. Further dis-cussion of dynamic bipolar circuit operation is presented in Chap. 4.

Shifting our attention to MOS circuitry we find that the basic flip-flop is also employed for statically operated RAMs and shift registers. Examples are shown in Fig. 2.4a and b, respectively. The trend, however, as evidenced by numerous commercial products, is to dynamic operation with device count and silicon area per bit effectively reduced. An example of one type of dynamic shift register is shown in Fig. 2.5 (cf Chap. 3). A number of dynamic RAM circuits are now commercially available, and the basic circuitry for these 4-, 3-, and I-MOS transistor dynamic RAM cells is shown in Fig. 2.6a~ b, and c~ respectively. The design and application of these cells will be presented in Chaps. 5 and 10, respectively. Discus-sion in this chapter focuses on fabricational aspects of these circuit elements.

The MOS ROM is similar to its bipolar counterpart because of its extreme simplicity (Fig. 2.7). Resulting MOS ROM cells are small (l transistor per cell) and, as with bipolar, many more bits of MOS ROM can be fabricated on a given size silicon chip than for MOS RAM and sequentially accessed memory circuits.