The DRAM interface allows the following conditions to be selected. Although DRAM can be used in areas 8 and 7 or areas 14 and 13, these condition are applied to all four areas and cannot be set individually for each area.
Table II-4.17 DRAM Interface Parameters
Parameter Selectable condition Initial setting Control bits
Page mode EDO page mode
or Fast page mode
Fast page mode REDO(DC)/Bus control register(0x4812E)
RAS mode Successive RAS mode
or Normal mode
Normal mode CRAS(D8)/DRAM timing set-up register(0x48130) Column address size 8, 9, 10 or 11 bits 8 bits RCA[1:0](D[B:A])/Bus control register(0x4812E) Refresh enable Enabled or Disabled Disabled RPC2(D9)/Bus control register(0x4812E)
Refresh method Self-refresh
or CBR refresh
CBR refresh RPC1(D8)/Bus control register(0x4812E)
Refresh RPC delay 2.0 or 1.0 1.0 RPC0(D7)/Bus control register(0x4812E)
Refresh RAS pulse width 2, 3, 4 or 5 cycles 2 cycles RRA[1:0](D[6:5])/Bus control register(0x4812E) Number of RAS precharge
cycles
1, 2, 3 or 4 cycles 1 cycle RPRC[1:0](D[7:6])/DRAM timing set-up register(0x48130) CAS cycle control 1, 2, 3 or 4 cycles 1 cycle CASC[1:0](D[4:3])/DRAM timing set-up register(0x48130) RAS cycle control 1, 2, 3 or 4 cycles 1 cycle RASC[1:0](D[1:0])/DRAM timing set-up register(0x48130)
Page mode
The DRAM interface allows EDO DRAM to be connected directly. Therefore, the EDO-page mode is supported along with the fast-page mode.
Use REDO to choose the desired page mode that suits the DRAM to be used.
REDO = "1": EDO page mode REDO = "0": Fast page mode (default) Successive RAS mode
For applications that require high-speed DRAM access, the DRAM interface supports a successive RAS mode. In this mode, even when successive accesses to the DRAM are not requested by the CPU or DMA, the
#RAS signal is kept low and operation is continued without inserting any precharge cycle. Therefore, when accessing the same page (row address) of the DRAM that has been accessed previously, the page mode remains active, allowing read/write to be performed at high speeds.
However, to maintain the rated AC characteristics, one idle cycle is inserted when access in the page mode is begun and when finished.
CRAS is used to set the successive RAS mode.
CRAS = "1": Successive RAS mode CRAS = "0": Normal mode (default)
The successive RAS mode is suspended by one of the following causes:
• a refresh cycle has occurred;
• bus control is requested by an external bus master;
• the requested device and page are not compatible with DRAM memory; and
• the slp or halt instruction is executed.
If the successive RAS mode is suspended, a precharge cycle is inserted before the next bus cycle begins.
Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and
#DWE for the low-byte write signal.
Column address size
When accessing DRAM, addresses are divided into a row address and a column address as they are output.
Choose the size of this column address using RCA, as shown below.
Table II-4.18 Column Address Size RCA1 RCA0 Column address size
1 1 11
1 0 10
0 1 9
0 0 8
The initial default size is 8 bits. Choose the desired size according to the address input pins of the DRAM to be used.
The row addresses output synchronously with falling edges of the #RAS signal are derived from the CPU's internal 28-bit addresses by logically shifting them to the right by an amount equal to the column address size. The MSB contains a 1. The column addresses are output to the address bus along with the falling edges of the #CAS signal. These addresses are derived directly from the CPU's internal 28-bit addresses.
Figure II-4.29 shows the contents of the row addresses thus output.
28-bit CPU internal address
T = "1", 0–27: Bit number of CPU internal address 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (1) Row address when column address is set to 8 bits
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
T T T T T T T T
(2) Row address when column address is set to 9 bits
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
T T T T T T T T
(3) Row address when column address is set to 10 bits
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
T T T T T T T T
(4) Row address when column address is set to 11 bits
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
T T T T T T T T
T
T
T T
T T
Figure II-4.29 Example of Row/Column Address Mapping Refresh enable
Use RPC2 to enable or disable the internal refresh function.
RPC2 = "1": Enabled
RPC2 = "0": Disabled (default)
After choosing the desired refresh method using RPC1, write "1" to RPC2.
Refresh method
The DRAM interface supports both a CAS-before-RAS refresh cycle and a self-refresh cycle. Choose the desired method using RPC1.
RPC1 = "1": Self-refresh
RPC1 = "0": CAS-before-RAS refresh
The generation interval of the CAS-before-RAS refresh is determined by the underflow signal of an 8-bit programmable timer 0. Consequently, before the CAS-before-RAS refresh can be executed, the 8-bit programmable timer 0 must be set to obtain the necessary underflow timing. When this method is selected and RPC2 is enabled, the refresh cycle is generated each time the 8-bit programmable timer 0 underflows.
The self-refresh is started by writing "1" to RPC2 while RPC1 = "1" and is terminated by clearing RPC1 or RPC2 to "0".
Refresh RPC delay
Use RPC0 to set the RPC delay value of a refresh cycle (a delay time from the immediately preceding precharge to the fall of #CAS).
RPC0 = "1": 2 cycles RPC0 = "0": 1 cycle Refresh RAS pulse width
Use RRA to set the #RAS pulse width of a CAS-before-RAS refresh cycle.
Table II-4.19 Refresh RAS Pulse Width RRA1 RRA0 Pulse width
1 1 5 cycles
1 0 4 cycles
0 1 3 cycles
0 0 2 cycles
The initial default value is 2 cycles.
Number of RAS precharge cycles
Use RPRC to choose the number of RAS precharge cycles.
Table II-4.20 Number of RAS Precharge Cycles RPRC1 RPRC0 Number of cycles
1 1 4 cycles
1 0 3 cycles
0 1 2 cycles
0 0 1 cycle
The initial default value is 1 cycle.
CAS cycle control
Use CASC to choose the number of CAS cycles when accessing DRAM.
Table II-4.21 Number of CAS Cycles CASC1 CASC0 Number of cycles
1 1 4 cycles
1 0 3 cycles
0 1 2 cycles
0 0 1 cycle
The initial default value is 1 cycle.
RAS cycle control
Use RASC to choose the number of RAS cycles when accessing DRAM.
Table II-4.22 Number of RAS Cycles RASC1 RASC0 Number of cycles
1 1 4 cycles
1 0 3 cycles
0 1 2 cycles
0 0 1 cycle
The initial default value is 1 cycle.