Data Arrangement in Memory
The E0C33 Family of devices handle data in bytes (8 bits), half-words (16 bits), and words (32 bits). When accessing data in memory, it is necessary to specify a boundary address that conforms to the data size involved.
Specification of an invalid address causes an address error exception. For instructions (e.g., stack manipulation or branch instructions) that rewrite the SP (stack pointer) or PC (program counter), the specified addresses are forcibly modified to appropriate boundary addresses. Therefore, no address error exception occurs in this type of instruction. For details about the address error exception, refer to the "E0C33000 Core CPU Manual".
Table II-4.12 shows the data arrangement in memory, classified by data type.
Table II-4.12 Data Arrangement in Memory Data type Arranged location Byte data Byte boundary address (all addresses) Half-word data Half-word boundary address (A[0]="0") Word data Word boundary address (A[1:0]="00")
The half-word and word data in memory area accessed in little-endian format by default. It can be changed to big-endian format using AxxEC (D[7:0])/Access control register (0x48132). When "1" is written to AxxEC, the corresponding area is accessed in big-endian method. The bit names and the corresponding areas are as follows:
A18EC (D7): Areas 17 and 18 A16EC (D6): Areas 15 and 16 A14EC (D5): Areas 13 and 14 A12EC (D4): Areas 11 and 12
A10EC (D3): Areas 9 and 10 ... Fixed at "0" (little-endian) for booting.
A8EC (D2): Areas 7 and 8 A6EC (D1): Area 6 A5EC (D0): Areas 4 and 5
To increase memory efficiency, try to locate the same type of data at continuous locations on exact boundary addresses in order to minimize invalid areas.
Bus Operation of External Memory
The external data bus is 16-bits wide. For this reason, more than one bus operation occurs depending on the device size and the data size of the instruction executed, as shown in Table II-4.13.
Table II-4.13 Number of Bus Operation Cycles Data size to
be accessed Devise
size Number of bus
operation cycles Remarks
32 bits 16 bits 2
16 bits 16 bits 1
8 bits 16 bits 1 In little-endian method, the low-order byte is accessed when the LSB of the address (A[0]) is "0" or the #BSL signal is L. The high-order byte is accessed when the LSB of the address (A[0]) is "1" or the #BSH signal is H.
In big-endian method, the high-order byte is accessed when the LSB of the address (A[0]) is "0" or the #BSL signal is L. The low-order byte is accessed when the LSB of the address (A[0]) is "1" or the #BSH signal is H.
32 bits 8 bits 4 In little-endian method, the 8-bit device must be connected to the low-order 8 bits of the data bus. In big-endian method, the 8-bit device must be connected to the high-order 8 bits of the data bus.
16 bits 8 bits 2 In little-endian method, the 8-bit device must be connected to the low-order 8 bits of the data bus. In big-endian method, the 8-bit device must be connected to the high-order 8 bits of the data bus.
8 bits 8 bits 1 In little-endian method, the 8-bit device must be connected to the low-order 8 bits of the data bus. In big-endian method, the 8-bit device must be connected to the high-order 8 bits of the data bus.
The following diagram shows sample bus operations where the A0 system is used.
Byte 1
A[1:0]=10 A[1:0]=00
15 2 0 15 1 0
Source (general-purpose register)
Destination (16-bit device)
Bus operation Little-endian
A[1:0]=00 A[1:0]=10
15 1 0 15 2 0
Source (general-purpose register)
Destination (16-bit device)
Bus operation Big-endian
Figure II-4.7 Word Data Writing to a 16-bit Device
Byte 1 Bus operation
1 2
Byte 3 Byte 2 Byte 1 Byte 0
31 Destination (general-purpose register) 0
A[1:0]=10 A[1:0]=00
Source (16-bit device)
15 0 15 0 Bus operation
2 1
Byte 3 Byte 2 Byte 1 Byte 0
31 Destination (general-purpose register) 0
A[1:0]=00 A[1:0]=10
Source (16-bit device)
15 0 15 0
Big-endian
Figure II-4.8 Word Data Reading from a 16-bit Device
Byte 1
Source (general-purpose register)
Destination (16-bit device)
Bus operation Little-endian
Source (general-purpose register)
Destination (16-bit device)
Bus operation Big-endian
Figure II-4.9 Half-word Data Writing to a 16-bit Device
Byte 1
Bus operation 1
Sign or Zero extension Byte 1 Byte 0 31 Destination (general-purpose register) 0
A[1:0]=∗0 Source (16-bit device)
0
Bus operation 1
Sign or Zero extension Byte 1 Byte 0 31 Destination (general-purpose register) 0
Big-endian
Byte 0
Data retained Byte 0 Data retained
Byte 3 Byte 2 Byte 1 Byte 0
Source (general-purpose register)
Destination (16-bit device)
Bus operation Little-endian
Data retained Byte 0 Data retained
Byte 3 Byte 2 Byte 1 Byte 0
Source (general-purpose register)
Destination (16-bit device)
Bus operation Big-endian
Figure II-4.11 Byte Data Writing to a 16-bit Device
RD byte
15 Data bus 0 RD byte Ignored
RD byte
31 0
A[1:0]=∗0 A[1:0]=∗1
1' 0 15 1
Bus operation Sign or Zero extension
Destination (general-purpose register)
Source (16-bit device) Little-endian
RD byte
15 Data bus 0 RD byte Ignored
RD byte
31 0
A[1:0]=∗1 A[1:0]=∗0
1' 0 15 1
Bus operation Sign or Zero extension
Destination (general-purpose register)
Source (16-bit device) Big-endian
Figure II-4.12 Byte Data Reading from a 16-bit Device
Data retained
15 Data bus 0 Data retained Byte 1 Data retained Byte 2 Data retained Byte 3
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=10 A[1:0]=00
A[1:0]=11 A[1:0]=01
8 4 08 08 08 1 0
Source (general-purpose register)
Destination (8-bit device)
3 2
Bus operation
(X: Not connected/Unused) Little-endian
Data retained Byte 2 Data retained Byte 1 Data retained Byte 0 Data retained
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=01 A[1:0]=11
A[1:0]=00 A[1:0]=10
8 1 08 08 08 4 0
Source (general-purpose register)
Destination (8-bit device)
2 3
Bus operation Big-endian
Figure II-4.13 Word Data Writing to an 8-bit Device
Ignored Ignored Byte 1 Ignored Byte 2 Ignored Byte 3
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=10 A[1:0]=00
A[1:0]=11 A[1:0]=01
8 4 08 3 08 2 08 1 0
Bus operation
(X: Not connected/Unused) Destination (general-purpose register)
Source (8-bit device) Little-endian Byte 2 Ignored Byte 1 Ignored Byte 0 Ignored
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=01 A[1:0]=11
A[1:0]=00 A[1:0]=10
8 1 08 2 08 3 08 4 0
Bus operation Destination (general-purpose register)
Source (8-bit device) Big-endian
Figure II-4.14 Word Data Reading from an 8-bit Device
Data retained Data retained Byte 1
Byte 3 Byte 2 Byte 1 Byte 0
Source (general-purpose register)
Destination (8-bit device) 2
Bus operation
(X: Not connected/Unused) Little-endian
Data retained Byte 0 Data retained
Byte 3 Byte 2 Byte 1 Byte 0
Source (general-purpose register)
Destination (8-bit device) 1
Bus operation
(∗: Uniformly 1 or 0) Big-endian
Figure II-4.15 Half-word Data Writing to an 8-bit Device
Ignored Ignored Byte 1 Byte 1 Byte 0
Bus operation
(X: Not connected/Unused) Destination (general-purpose register)
Source (8-bit device) Sign or Zero extension
Little-endian Byte 0 Ignored Byte 1 Byte 0
31 0
A[1:0]=∗1
A[1:0]=∗0 0
8 1 08 0
Bus operation Destination (general-purpose register)
Source (8-bit device) Sign or Zero extension
Big-endian
(∗: Uniformly 1 or 0) Figure II-4.16 Half-word Data Reading from an 8-bit Device
Data retained
15 Data bus 0 Source (general-purpose register)
Destination (8-bit device)
Bus operation
(X: Not connected/Unused) Little-endian
1 Data retained
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=∗∗
1 0 8 Source (general-purpose register)
Destination (8-bit device)
Bus operation Big-endian
Figure II-4.17 Byte Data Writing to an 8-bit Device
Ignored
Bus operation
(X: Not connected/Unused) Destination (general-purpose register)
Source (8-bit device) Sign or Zero extension
Little-endian
1 Ignored
Byte 0
31 0
1
Bus operation Destination (general-purpose register)
Sign or Zero extension Big-endian