ADDITIONAL FIELD DESCRIPTIONS
Q: DATE/TIME T:IERMINATE
DUG - RUN INIT
ENTER REQUEST ACCORDING TO THE DIAG.MENU
DIAG==> AH ADPI==> LINE==> OPT==> N
CCU DIAGNOSTIC GROUP RUNNING TIME
When the diagnostic request is 2, the total running time is 18 minutes 50 seconds.
MANUAL INTERVENTION ROUTINES
• Routine AB02 is used when scoping between the MOSS and the
eeu.
• Routine AB03 is used to provide a FRU List for a
ceu
hardcheck failure.
• Routine BI04 is used when scoping the CCU storage.
• Routine BIOS is used to test the remote power off capability.
Routines AB02, AB03, BI04, and BI05 will not run unless specifically selected.
OPTION SELECTION RESTRICTION
Loop on error is not allowed when an error occurs in routine BK04.
Manually-Invoked Routines
• Routine AJOI is used when the standard
eeu
diagnostic group does not isolate the failure. See in the MIM Part 2,Chapter 3, the CCU extended replacement procedure.
• Routine BOOI is used to analyse the
ceu
storage.Routines AJOI and B001 will not run unless specifically selected.
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"ANUAL SELECTION RESTRICTIONS
Routines DA61. DB67. DC6F and DD76 must not be selected. These routines check that the general purpose register contents set by routines DAO!. DB02. DC03. and DD04 have not changed after the CCU instruction set is tested.
Routine BJ03 must not be selected; it uses information from BJ02.
DIRECT OPERATION - 1FT A
RUNNING TIttE
This 1FT is loaded in the MOSS storage and tests the MIOC card using direct operations. The following are tested:
• MCC/MIOC card connection
• LSSD mechanism (ending with the CCU LSSD initialization)
• High/low level interrupt request functions
• MIOC parity circuits
• Registers that can be read/written with direct operations
• Hardcheck error path
• Interrupt disable functions
• CCU hardstop bypass function
• MDOR (on DFLl-x cards)
• CCU-to-MOSS status registers E and F
Run Init 10 sec
AA 9 sec
AB 3 sec
AC 11 sec
AD 7 sec
AE 15 sec
AF 7 sec
AG 9 sec
AH 10 sec
AI 18 see
AJ Manually invoked AK 1 min 46 sec Total 3 min 25 sec
HANUAL INTERVENTION ROUTINES
AB02: MOSS-to-CCU seoping
AB03: CCU BERs analysis procedure ttanually-Invoked Routine
AJ01: CCU SRl test with initial values ttESSAGES
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INDIRECT OPERATION - 1FT B
This 1FT is loaded in the MOSS storage and tests the MIOC card using operations. The following are tested:
• Branch trace/address compare registers
• Local stores
• CCU data flow registers
• Wrap branch trace mechanism
• Input and output X'7X' instructions
• Storage scanning
• ECC mechanism
• CCU main storage
• Remote power off
Run Init 10 sec BA 1 min 15 sec
BB 18 sec
BC 5 sec
BD 7 sec
BE 5 sec
BF 6 sec
BG 3 min 58 sec
BH 3 sec
BI 3 sec
BJ 33 sec
BK 1 min 14 sec
BL 14 sec
BM 10 sec
BN 6 sec
BOOI manually invoked Total 8 min 27 sec
MANUAL INTERVENTION ROUTINES
BI04: CCU/Storage Scoping Routine BIOS: Network Power Off Test Manually-Invoked Routine
BOOl: storage Solid I-Bit Error Detection MESSAGES
None
BASIC INSTRUCTION - 1FT C
RUNNING TIME
MESSAGES
This 1FT is loaded into the MOSS storage together with an 1FT responder in the CCU storage. It verifies the basic instruction set step-by-step.
Run Init 56 sec
CA 8 sec
C8 11 sec
CC 8 sec
CD 8 sec
CE 8 sec
CF 7 sec
CG 9 sec
CH 8 sec
Total 2 min 3 sec
None
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FULL INSTRUCTION - 1FT D
This 1FT is loaded into the MOSS storage together with an 1FT responder in the CCU storage.
It exercises the full instruction set at every interrupt level.
It checks the general registers and the changing of the interrupt level.
This 1FT does not exercise IOH and IOHI instructions.
• The 'IOHI' instruction is tested with the IOC bus IFTs.
• The 'IOH' instruction is tested with the RDV IFTs.
Note: The 'Exit' instruction is tested with interrupt level swapping in the routines of the DA80 series of this 1FT.
SPECIAL SEQUENCE OF 1FT D ROUTINES
HESS AGES
The routines of this 1FT are listed in the sequence of the routine number, not taking into account the section. For example, DA80 is after DD78.
In the routine numbers. DX means DA. DB. DC. DD. or DE. (For example. DXIO refers to DAIO. DBIO. DCIO. DDIO. or DEIO.
Run Init 10 sec
DA 51 sec
DB 47 sec
DC 48 sec
DD 48 sec
DE 44 sec
Total 4 min 8 sec
None
FULL STORAGE - 1FT E
Running Ti_
Messages
This 1FT is loaded into the CCU storage and responds to the diagnostic control monitor (DeM) requests through the
communication processor (CP) in the MOSS.
This 1FT tests the storage extensively,
Run Init 10 sec
EA 17 sec
EB 4 sec
Total 31 sec
None
BRANCH TRACE'ADDRESS COMPARE - 1FT F
RUNNING TIME
MESSAGES
This 1FT is loaded into the CCU storage and responds to the diagnostic control monitor (DeM) requests through the
communication processor (CP) in the MOSS.
This 1FT tests the storage extensively.
Run Init 10 sec
FA 4 sec
Total 14 sec
None
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ROUTINES DESCRIPTION
AAOI - MOSS INOPERATIVE TEST
ERC
D700 Verify
0701 Analyse 0702
0703 0705 0706 0707
When the MOSS inoperative bit is set in the MCC Status Register 1. the MIOC/MCC card is disabled. Any read operation causes a level 0 interrupt.
1. To perform the test. interrupts to the MOSS are disabled.
and MOSS inoperative is set in the MCC Status Register 1.
2. Read from address 0 and check the expected interrupt level O.
Function Error Description RAC Comments
interrupt level 0 No interrupt occurred and 802 no bit is set in MCC Status Register 2.
MCC Status Register CCU parity check bit on 803
"
MIOC/MOSS parity bit on 803"
CCU parity check and MIOC/ 805MOSS parity bits on
"
CCU/MOSS timeout and CCU 802parity check bits on
"
CCU/MOSS timeout and 802MIOC/MOSS parity bits on
"
CCU/MOSS timeout and 805MIOC/MOSS parity and CCU parity check bits on
AA02 - CCU PARITY CHECK LINE TEST (PART 1)
ERC 0700
0701 0702 0703 0706
This routine checks that the setting of the Interrupt Test bit in MCC Status Register 2 raises a CCU parity check bit inMCC Status Register 2 when a read operation is performed. The Interrupt Test bit forces bad parity on the MIOC Address Bus.
1. Set Interrupt Test bit in MCC Status Register 2.
2. Read from address 0 and check the interrupt level O.
3. Verify other possible events in MCC Status Register 2 that could cause an interrupt level O.
Function Error Description RAC Comments
Test interrupt level 0 No interrupt level 0 802
Read MCC Status Register 2 EXP DATA and RCV
for level 0 interrupt due DATA fields
to: contain
- CCU/MOSS timeout respectively
- MIOC/MOSS parity check expected value
- CCU parity check and received
value of MCC status Register
CCU parity check 802
MIOC/MOSS parity check 804 MIOC/MOSS parity check and 803 CCU parity check
CCU/MOSS timeout and 840 MIOC/MOSS parity check
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AA03 - CCU PARITY CHECK LINE TEST (PART 2)
ERC 0700
0701 0702 0703 0706 0707
This routine checks that setting the Interrupt Test bit in the Mee status Register 2 raises a ecu Parity Check bit in MCC Status Register 2 when a write operation is performed. The Interrupt Test bit forces bad parity on the MIOC Address Bus.
1. Set the Interrupt Test bit in the MCC Status Register 2.
2. Write to address 0 and check the interrupt level O.
3. Verify other possible events in MCC Status Register 2 that could cause an interrupt level O.
Fund:i on Error Description RAC Comments
Test interrupt level 0 No interrupt level 0 802
Read MCC Status Register 2 EXP DATA and RCV
for level 0 interrupt due DATA fields
to: contain
- CCU/MOSS timeout respectively
- MIOC/MOSS parity check expected value
- CCU parity check and received
value of MCC Status Register
ceu parity check 803
MIOC/MOSS parity check
MIOC/MOSS parity check and 805 CCU parity check
CCU/MOSS timeout and 802 MIOC/MOSS parity check
CCU/MOSS timeout. MIOC/MOSS 805 parity check and CCU parity check
AAO~ - "CC/HIDC TEST (PART 1)
ERC
0700 Read data Interrupt 0701
0702 0704
This routine checks the parity checker and part of the address/data bus.
1. Read direct operation from address 0 and check the data which must be equal to 0 (no active bits on bus).
2. Any address/data bus parity error causes a level 0 interrupt.
Function Error Description RAC Comments
from address 0 Data not equal to 0 811
level 0 occurred 803 ADDIT INFO fi eld
displays the CCU parity check contents of MCC
status register MIOC/MOSS parity check 803 2
CCU/MOSS timeout 806
AA05 - HCC/HIDC TEST (PART 2)
ERC
Check for 0701
0702 0704 0705
This routine checks the parity checker and part of the address/data bus by writing (to address 0) a series of data patterns of floating zeros and ones and a pattern to exercise all the gates in the parity checker.
Function Error Description RAC Comments
level 0 interrupt ADDIT INFO field
displays the CCU parity check 803 contents of MCC
status register MIOC/MOSS parity check 803
CCU/MOSS timeout 806
CCU/MOSS timeout and CCU 802 parity check