(1) Turning A/D converter ON/OFF
The power supply to the circuit of the A/D converter is normally kept OFF, in order to reduce current consumption. The A/D converter starts when "1" is written into the register ADON and continues to operate until a "0" has been written. It terminates A/D conversion when a "0" has been written into the ADON and the circuit also goes OFF.
The ADON can be read and is "1" while the circuit is operating and is "0" when it is stopped.
When "1" is written into the ADON, it resets the dual slope counter to "0" and executes the A/D conversion sequence from auto zero adjustment. Writing "1" into ADON is also effective during A/D conversion and it terminates the sequence during the current execution and starts a new A/D conversion sequence.
ADON write signal ADON register A/D converter circuit Integral AMP output
1 1 0
ON
Reset Fig. 4.12.16
Control of A/D conversion by the ADON register
A/D interrupt
When it terminates the integration of the analog input and starts the reverse integration according to the reference voltage, the dual slope counter is counted up from "0". At the point where the integral AMP output due to the reverse integration has crossed "0", the count stops and the data of the dual slope counter is latched.
When the reverse integration period has terminates, the A/D interrupt factor flag IAD is set to "1" and an interrupt occurs.
The A/D interrupt can also be masked by writing a "0" into the interrupt mask register EIAD. When EIAD is set to "1", an interrupt occurs.
The interrupt factor flag IAD is set to "1" when the reverse integra-tion period has terminates, regardless of the setting of the interrupt mask register and is reset to "0" by reading.
(2)
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
(3) Wait time for A/D conversion
To perform a stable A/D conversion, the following wait times are necessary.
• In the case of voltage measurement mode and differential voltage measurement mode
Take 300 msec or more wait time from the beginning of the refer-ence voltage VR1 generation or impressing from outside to the end of an input integration period. (Satisfy the regulation time by delaying the timing of the A/D converter ON.)
• Resistance measurement mode
Take a time that is calculated by the following expression or more from turning the A/D converter ON to the end of the input integra-tion period. (The A/D converted data until the calculated time has passed is invalid.)
10 × 0.1 µF (capacitance for VR, -VR generation circuit) × R (Rref + 130 kΩ) (4) Reading of the A/D conversion result
The dual slope counter is a 13-bit binary counter and is counted up from "0" to the reverse integration period. The result that has been counted is latched upon completion of the reverse integration period and the data from that latch can be read. This data AD0–
AD12 is allocated to the address F7H–FAH. The register ADP that indicates the polarity of the analog input voltage is allocated to FAH, in addition to the AD12 (MSB of the data).
When the analog input is positive (+) the ADP becomes "1" and when it is negative (-) it becomes "0".
The latched data is effective until the next A/D conversion is completed and it is necessary to read up to that point. Basically you should process the read processing by the A/D interrupt.
Moreover, you should read the data in order of F7H → F8H → F9H
→ FAH from the lower side. This is due to the following reason.
When the following A/D conversion terminates during data read-ing, the latched data is just rewritten. For this reason, the IDR bit is set into the address FBH, so that it can decide whether the data read is effective or invalid, by reading the IDR bit following the reading of data. When the reading of the data in the above se-quence has been completed prior to the termination of the next A/
D conversion, the IDR becomes "0", indicating that the data is effective. When the following A/D conversion has been terminated and the latch rewritten before the reading terminates, the IDR becomes "1", indicating that the data is invalid.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Take care that conversion data may sometime become invalid by turning the A/D converter OFF (including resetting). In this case, as it is "0" the IDR is not set. When reading data after turning the A/D converter OFF, the A/D converter should be OFF in the period from an interrupt generation to the beginning of a reverse integra-tion.
You should process the read data using software, such that is becomes the object volume.
The voltage value (voltage measurement and differential voltage measurement) and resistance value (resistance measurement) for each count of read data becomes as follows according to the resolution.
Resolution Voltage value for each count Resistance value for each count 6,552 50 µV (163.8 mV/3,276) Rref / 3,276
3,276 100 µV (163.8 mV/1,638) Rref / 1,638
1,638 200 µV (163.8 mV/819) Rref / 819
820 400 µV (163.8 mV/410) Rref / 410
Correction is necessary when inputting voltage through the attenuator circuit. When A/D conversion is done by connecting a sensor or the like, it will have individual sensor characteristics between the sensor detection volume and the voltage or the resist-ance, so you should use software to do the conversion according to those characteristics.
Figure 4.12.17 shows a flow chart of the data conversion and data reading and Figure 4.12.18 shows a timing chart for the A/D conversion.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Measurement mode and input terminal setting
Reference voltage generation circuit setting
Middle electric potential generation circuit setting Start A/D conversion
(Set ADON to "1")
A/D interrupt
Read <F7H>
Read <F8H>
No
Yes A/D conversion
Read <F9H>
Read <FAH>
Read IDR <FBH>
IDR = "0"
Data processing
Complete
No Yes
No
Yes
END Stop A/D conversion
(Set ADON to "0") 1
1
2 2
Fig. 4.12.17 A/D conversion flow chart
Integral AMP output Interrupt
Data read Data read Data read Data read IDR read IDR register
OK NG
<F7>
<F8>
<F9>
<FA>
<FB>
Fig. 4.12.18 A/D conversion timing chart
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Table 4.12.4 shows the A/D converter control bit and its address.