cvo
R 1 ,02 eX 2 , B 2 ) [RX]'4E'
I
R1I
X2I
B2 020 8 12 16 20 31
The radix of the first operand is changed from binary to decimal, and the result is stored at the second-operand location. The first operand is treated as a 32-bit signed binary integer.
The result occupies eight bytes in storage and is in the format for packed decimal data, as described in Chapter 8, "Decimal Instructions." The
low-order four bits of the result represent the sign.
A positive sign is encoded as 1100; a negative sign is encoded as 1101.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (store, operand 2) Programming Notes
1. An example of the use of CONVERT TO DECIMAL is given in Appendix A.
2. The number to be converted is a 32-bit signed binary integer obtained from a general register.
Since 15 decimal digits are available for the result, and the decimal equivalent of 31 bits requires at most 10 decimal digits, an overflow cannot occur.
DIVIDE
DRo
8 12 15, 50 '
I
R 1I
X2I
B2o
8 12 16 20 31The doubleword first operand (the dividend) is divided by the second operand (the divisor), and the remainder and the quotient are placed in the first-operand location.
7-16 IBM 4300 Processors Principles of Operation
The R 1 field of the instruction specifies an even-odd .pair of general registers and must designate an even-numbered register. When Rl is odd, a specification exception is recognized.
The dividend is treated as a 64-bit signed binary integer. The divisor, the remainder, and the quotient are treated as 32-bit signed binary integers. The remainder and quotient replace the dividend in the pair of registers specified by the R 1
field. The remainder is placed in the
even-numbered register, and the quotient is placed in the odd-numbered register.
The sign of the quotient is determined by the rules of algebra. The remainder has the same sign as the dividend, except that a zero quotient or a zero remainder is always positive. When the magnitUdes of the dividend and divisor are such that the quotient cannot be expressed by a 32-bit signed binary integer, a fixed-point-divide
exception is recognized, and the operation is suppressed.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2 of D only) Fixed-Point Divide
Specification
EXCLUSIVE OR
XR
o
8 12 15x
[RX]o 8 12 16 20
XI [S I]
'97'
o 8 16 20
31
31
xc
[SS]r---.---~--~-/--~--~-/
' - - - - _ I D_7 _ I - l . . -_ _ L
_LI
_B1---L1_~ 1
B 2~~
o
8 16 20 32 36 47The EXCLUSIVE OR of the first and second operands is placed in the first-operand location.
The connective EXCLUSIVE OR is applied to the operands bit by bit. A bit position in the result is set to one if the corresponding bit positions in the two operands are unlike; otherwise, the result bit is set to zero.
For XC, each operand is processed left to right.
When the operands overlap, the result is obtained as if the operands were processed one byte at a time and each result byte were stored immediately after the necessary operand byte is fetched.
For XI, the first operand is one byte in length, and only one byte is stored.
Resulting Condition Code:
o
Result is zero 1 Result is not zero 23
Program Exceptions:
Access (fetch, operand 2, X and XC; fetch and store, operand 1, XI and XC)
Programming Notes
1. An example of the use of EXCLUSIVE OR is given in Appendix A.
2. The instruction EXCLUSIVE OR may be used to invert a bit, an operation particularly useful in testing and setting programmed binary bit switches.
3. A field EXCLUSIVE-ORed with itself becomes all zeros.
4. For XR, the sequence A EXCLUSIVE-OR B B EXCLUSIVE-OR A, A EXCLUSIVE-OR B ' results in the exchange of the contents of A and B without the use of an additional general register.
5. Accesses to the first operand of XI and XC consist in fetching a first-operand byte from storage and subsequently storing the updated value. These fetch and store accesses to a particular byte do not necessarily occur one immediately after the other. Thus, the instruction EXCLUSIVE OR cannot be safely
used to update a location in storage if the possibility exists that another CPU or a channel may also be updating the location. An example of this effect is shown for the instruction OR (01) in the section "Multiprogramming and Multiprocessing Examples" in Appendix A.
EXECUTE
1441
I
R 1I
X2I
B2 D2o 8 12 16 20 31
The single instruction at the second-operand address is modified by the contents of the general register specified by R 1, and the resulting target instruction is executed.
When the R 1 field is not zero, bits 8-15 of the instruction designated by the second-operand address are ORed with bits 24-31 of the register specified by R l' The ~Ring does not change either the contents of the register specified by R1 or the instruction in storage, and it is effective only for the interpretation of the instruction to be executed.
When the R1 field is zero, no ORing takes place.
The target instruction may be two, four, or six bytes in length. The execution and exception handling of the target instruction are exactly as if the target instruction were obtained in normal sequential operation, except for the instruction address and the instruction -length code.
The instruction address of the current PSW is increased by the length of EXECUTE. This updated address and the instruction-length code of EXECUTE are used, for example, as part of the link information when the target instruction is BRANCH AND LINK. When the target
instruction is a successful branching instruction, the instruction address of the current PSW is replaced by the branch address specified by the target instruction.
When the target instruction is in turn an EXECUTE, an execute exception is recognized.
The effective address of EXECUTE must be even; otherwise, a specification exception is recognized. When the target instruction is two or three halfwords in length but can be executed without fetching its second or third halfword, it is unpredictable whether access exceptions are recognized for the unused halfwords. Access exceptions are not recognized for the
second-operand address when the address is odd.
Chapter 7. General Instructions 7 -17
Condition Code: The code may be set by the target instruction.
Program Exceptions:
Access (fetch, target instruction) Execute
Specification Programming Notes
1. An example of the use of EXECUTE is given in Appendix A.
2. The ORing of eight bits from the general register with the designated instruction permits indirect length, index, mask, immediate-data, and register specification.
3. The fetching of the target instruction is considered to be an instruction fetch for purposes of program-event recording and for purposes of reporting access exceptions.
4. An access or specification exception may be caused by EXECUTE or by the target instruction.
S. When an interruptible instruction is made the target of EXECUTE, the program normally should not designate any register updated by the interruptible instruction as the R 1, X2, or B2 register for EXECUTE, since on resumption of execution after an interruption, or if the instruction is refetched without an interruption, the updated values of these registers will be used in the execution of EXECUTE. Similarly, the program should normally not let the
destination field of an interruptible instruction include the location of the EXECUTE, since the new contents of the location may be interpreted when resuming execution.
INSERT CHARACTER IC R1,D2(X2,B2) [RX]
'43'
I
R1I
X2I
B2 D20 8 12 16 20 31
The byte at the second -operand location is inserted into bit positions 24-31 of the general register designated by the R 1 field. The remaining bits in the register remain unchanged.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
7-18 IBM 4300 Processors Principles of Operation
INSERT CHARACTERS UNDER MASK ICM R1,M3,D2(B2) [RS]
'BF'
I
R1I
M3I
B2 D20 8 12 16 20 31
Bytes from contiguous locations beginning at the second-operand address are inserted into the first-operand location under control of a mask.
The contents of the M 3 field are used as a mask.
These four bits, left to right, correspond one for one with the four bytes, left to right, of the general register designated by the R 1 field. The byte positions corresponding to ones in the mask are filled, left to right, with bytes from successive storage locations beginning at the second-operand address. When the mask is not zero, the length of the second operand is equal to the number of ones in the mask. The bytes in the general register corresponding to zeros in the mask remain unchanged.
The resulting condition code is based on the mask and on the value of the bits insetted. When the mask is zero or when all inserted bits are zeros, the condition code is set to O. When the inserted bits are not all zeros, the code is set according to the leftmost bit of the storage operand: if this bit is one, the code is set to 1; if this bit is zero, the code is set to 2.
When the mask is not zero, exceptions associated with storage-operand access are recognized only for the number of bytes specified by the mask. When the mask is zero, access exceptions are recognized for one byte.
Resulting Condition Code:
o
All inserted bits are zeros, or mask is zero 1 Leftmost bit of the inserted field is one 2 Leftmost bit of the inserted field is zero, andnot all inserted bits are zeros 3
Program Exceptions:
Access (fetch, operand 2) Programming Notes
1. Examples of the use of INSERT
CHARACTERS UNDER MASK are given in Appendix A.
2. The condition code for INSERT
CHARACTERS UNDER MASK (ICM) is
defined such that, when the mask is 1111, the instruction causes the same condition code. to be set as for LOAD AND TEST. Thus, the instruction may be used as a storage-to-register load-and-test operation.
3. An rCM instruction with a mask of 1111 or 0001 performs a function similar to that of a LOAD (L) or INSERT CHARACTER (IC), respectively, with the exception of the condition -code setting. However, the performance of ICM may be slower.