-
C PC /iIIJl/D8ITcorp.
.
TAPEMASTER
Application Note
2405 Annapolis Lane Plymouth, MN 55441 (612) 559·2034
TAPEMASTER Application Note
Copyright Computer Products Corporation August 1981
Revision 01 "8-1-81
Publication Number 210200Q1
REVISION INFORMATION
Rev i s i on R e cord
Revi si on Date Cornmen t s
01 8-1-81 Initial Release
Revision Cross Reference
This document is revision date
--- - - - -
This document is valid for:
TAPEMASTER Firmware set
---
TAPEMASTER Board Number
---
Part Number
---
TABLE OF CONTENTS 1.0 OVERVIEW
2.0 TAPEMASTER START-UP CHECKLIST 3.0 INITIALIZATION
4.0 COMMAND EXECUTION 4.1 CONFIGURE
4.2 STATUS
4.3 DIRECT READ/WRITE 5.0 16-BIT SYSTEMS 6.0 OPTIONS
6.1 INTERRUPT S 6.2 LINK
6.3 BUS LOCK
6.4 CONTINUOUS TAPE 6.5 WIDTH
7.0 ERROR RECOVERY PROCEDURES 7.1 WRITE DATA ERROR
7.2 READ DATA ERROR 7.3 WRITE TIME-OUT 7.4 READ TIME-OUT 7.5 OVERRUN
7.6 BLANK TAPE READ 7.7 PARITY ERROR
8.0 TAPEMASTER COMMAND TEST
APPENDICES
1.0 OVERVIEW
This document is intended to aid the user in the
incor~orationof the CPC TAPEMASTER Tape Adaptor into a Multibus-based computer system. This document does not replace the TAPEMASTER Produc.t Specification, but is intended as a supplement to i t .
Section 1 provides a brief summary of the outline of this Appli- cation Note.
Section 2 is a check list of steps to perform to cause the TAPE- MASTER to execute commands in its repertoire.
Section 3,4 and 5 offer examples of various Parameter Blocks, pro- gram listings and flow charts for TAPEMASTER command execution.
Section 6 discusses the use of the TAPEMASTER control options.
Section 7 outlines error recovery procedures.
Section 8 outlines a complete TAPEMASTER Command Test.
The Appendices discuss several of the drives which the TAPEMASTER
con t ro 1 s .
2.0
TAPE~~STERSTART UP CHECKLIST
The purpose of this checklist is to aid the user in establishing communications between the CPC
TAPE~STERand the host system, and causing the
TAPE~STERto be ready to accept commands from the host. Refer to the
TAPE~STERProduct Specification and other sections of this document for details of the various steps below.
To incorporate the TAPEMASTER into a Multibus-based system, per- form the following steps:
I. Before applying power, set these straps on the board. Refer to the TAPEMASTER Product Specification, Appendix D. Retain the factory settings on all other jumpers.
A. Channel Attention/Board Reset (DIP Switch).
B. 8/16 bit system data bus (DIP Switch).
C. 8/16 bit I/O address (15-16).
D. Initialization Address (31-50).
E. Bus Arbitration (1-5, 51-53).
II. Insure that the host system properly handles all Multibus signals associated with Bus Priority. The
TAPE~STERwill operate in a serial or parallel priority system.
Ill. Assert a reset to the TAPEMASTER, either by activating the INIT/ line on the Multibus, or by executing an I/O write to
the
TAPE~~STERReset address.
IV. Set up the three control blocks necessary for the Initial- ization sequence and issue a Channel Attention. The TAPE- MASTER always executes an Initialization sequence when it
recieves the first Channel Attention after a reset. Ini- tialization is executed only once.
V. Set up any command Parameter Block, close the Gate and issue a Channel Attention. When the
TAPE~STERhas completed the command, it will open the Gate . . Do not proceed until this occurrs.
Begin with simpler commands ( Configure, NOP, Status) until
the TAPEMASTER operation becomes familiar.
3.0 INITIALIZATION
Before the TAPEMASTER can execute commands properly, it must be initialized. Initialization is the procedure which assigns per- manent values to some of the programmable addresses associated with command execution.
Itinvolves setting, up three short blocks
of data in system memory, and then issuing a Channel Attention to the
TAPEW~STER.The Initialization Blocks for a host system with an 8-bit data bus are shown in Fig. 3-1.
The addresses in this example are arbitrary and are all located in the lower 64K of system memory. However, they could be located anywhere in the lower 1M byte.
100BH 5005H 5027H
20 }---.
]----. 00 00
00 00
50 00 50 00 00
00 03 51 00
1006H FF 11
5020H
System Configuration Pointer
System Configuration Block
Channel Cont rol Block
Fig. 3-1 Initialization Blocks for an 8-bit system.
The System Configuration Pointer begins at 01006H, as directed by the associated jumpers. The first byte instructs the TAPEMASTER that the physical width of the system is 8 bits (00). The last four bytes are a Pointer, specifying the location of the System Configuration Block as 05000H to 05005H.
The first byte of the System Configuration Block must be 03H for proper operation. The last four bytes specify the location of the Channel Control Block as 05020H to 05027H.
The first byte of the Channel Control Block is the Channel Control Word (CCW). The CCW is set to IIH, since no interrupts are pend-
ing. The Gate, at OS021H, is set closed. The rest of the block
is unused during Initialization ..
At the completion of the Initialization process, using the example values of Fig. 3-1, the following have ,been accomplished:
A. The location of the Channel Control \'lord (CCVn is fixed at
OS020H (FS020H in Fig. 3-2). .
B. The location of the Gate is fixed at S021H (FS021H).
. ' .
.
c. ,The location of the Parameter 'Block ·(or first Parameter Block in a chain) will be sp-ecified by a p'ointer whose location is fixed at 5022H-5025H (F5020H-FS025H).
D.· The TAPEMASTER is· ready to accept commands~
Locations Oloo6H-0100BH and (F)5000H-(F)500SH may now be re-used if needed.. Locations (F)S020H-(F)5027H must remain dedicated to
TAPEMASTER control. .
Shown in Table 3-1 is an 8080/8085 program to execute the Initial-
ization
seq~enceof Fig. 3-1.
The steps which must be executed by the host CPU to accomplish the Initialization are outlined in Fig. 3-3.
NO
CONSTRUCT
·scp
CONSTRUCT
sca
CONSTRUCT
cca
ISSUE CA
Fig. 3-3 Initialization Process
The Initialization Blocks for a host system with a 16-bit data bus are shown in Fig. 3-2. These blocks are similar to Fig. 3-1, except that a 16-bit system is specified (Ol006H=Ol). This exam- ple also indicates how th'e blocks may be located beyond the 64K byte range by specifying non-zero values in the Pointer Bases.
100BH FO 00 50 00 01 1006H
System Configuration Pointer
F500S14
FO ,50
00 20
F5000H
System Configuration Block
F5027H"
FO 00
51 00
FF
11F5020H
Channel Control Block
Fig. 3-2 Initialization Blocks for a 16-bit system.
'TA"f'tA5TEIl SAMPLE "'~ITE ~O'JTlNE.' MACRO-AD 3.3" 17-MAR-AO PAGE I-I l..,;
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RET"RN COliN! E tEl n ADR OF e 0poMETER 'pl neK RUFFER ,SIZ~ FIELD ADR. OF PARAMETER ~LOCK.
RECORDS FIELD ADDRESS OF PARAMETER BLOCK.
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~~~~~
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03700 SHLD COMANO • 2 I UPPER WO~O OF COMMAND FIELO.
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.n.05200 SHLD COMAND I CO"I'AND FIELD := DIRECT WRITE.
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011400
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011600 OGATE?:
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__ ~Oul~5~?~ __ ~C~9 __________________ ~0~9Ul~0~0~ ________ ~~EET~ _________________________________________________________________________________ ~;I
09~00 ENO T~~ITE ~
Table 4-1. Tape Write Program
17-MAIl-80
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Table 3-1. Initialization Program
4.0 After Initialization, the
TAPEM~STERis ready to accept commands.
The general sequence of events to begin execution of commands are outlined in Fig. 4-1. Table 4-1 is an 8080/8085 program to exe- cute this sequence for a Tape/Write command outlined in section 4.3. Other commands would be similar.
The remaining paragraphs of this section present examples of sev- eral TAPEMASTER commands. It is assumed that the host system has an 8-bit data bus. Section 5 describes how these examples would differ for a 16-bit system.
For the sake of uniformity, all the examples in this section util- ize only the lower 64K of system memory (Pointer Base=OOOOH),
for Parameter Blocks and data blocks. However, they may be loca-
ted anywhere in the lower 1M byte. If the Page Register is loaded
with an appropriate value, all data blocks may then be located any-
where in the 16M byte addressing range of the
TAPE1~STER.no
CONSTRUCT PB(II)
CLOSE GATE
·CONSTRUCT CCB
ISSUE CA
Fig. 4-1 General Command Sequence
4.1 CONFIGURE
After Initialization, any command may be executed first. The Con- figure command is a logical choice to execute first, because it.
executes a brief micro-diagnostic, and also returns information of use to the system.
The associated Parameter Block for a Configure command (Fig. 4-2) occupies 22 bytes from 05100H to 05115H in system memory. The Pointer to this Parameter Block is located in the Channel Control Block.
I fthe Parameter Block location is to be moved, the Point- er may be changed after the processor has control of the TAPEMASTER
(closes an open Gate), and before issuing a Channel Attention.
Besides the command field, which is all zeros for a Configure com-.
mand, the only other Parameter Block entry required as input is the Control field. In this example, Control is all zeros. This indicates that no interrupt is to be generated at the completion of the command, and no other Parameter Block is linked. The re- maining bits, such as Tape Select, Reverse, etc., are ignored since
they do not apply.
After the Configure command has been executed and the Gate·opened by the TAPEMASTER, the Parameter Block will have been updated by
the
TAPE~ffiSTERas in Fig. 4-3a. There are two updates to be noted.
First, the Command Status byte contains a COHo Referring to the TAPEMASTER Product Specification, this indicates that the Parame-
ter Block was entered (E bit set) and successfully completed .(C bit set and zero error code).
The second update in the Parameter Block is
th~Return Count
field. The TAPEMASTER in this example has determined. that it con- tains 16K bytes of static RAM which may be used during buffered operations. This value (4000H) is returned in the Return Count field.
Fig 4-3b shows an example of how the Parameter Block might be up- dated in the case of an error. The Command Status byte (05011H)
indicates the Parameter Block was entered (E bit set) but not com-
pleted (C fuit not set when the Gate was opened). The 5-bit error
code indicates that a OEH error occurred. Referring to Appendix C
of the Product Specification, this error indicates that the TAPE-
MASTER recieved an error when calculating a checksum on the firm-
ware.
5115H
5111 H
00
51 GATE
xx xx xx
XX XX XX XX XX
00 00 00
00 00 11
xx xx xx
XX XX XX XX XX
00 00 00
}
5020H
I I I
510011
Fig. 4-2 Configure Command
CHANNEL CONTROL BLOCK
PARAMETER
BLOCK
4.2 STATUS
The Status command (28H) is the most basic command to execute.
The Parameter Block for Status is shown in Fig. 4-4". After the TAPEMASTER has executed the command it will update the Parameter Block as shown.
5115H 5115H
xx xx XX xx
xx xx " XX XX
5111H xx xx 511111 CO TS
xx xx XX XX
xx xx XX XX
xx xx xx xx
xx XX
,xx XX
xx XX "" xx XX
00 00 00 00
00 00 00 00
00 28 00 28
5100H 5100H
a} Before execution b} After execution Fig. 4-4 Status Parameter Block
The upper byte of Status (5111H) contains a COHo Ref"erring to the TAPEIV1ASTER Product Specification, this indicates that the Parameter Block was entered (E bit set), and successfully completed (C bit
set and no error code). TS represents Tape Status. In general,
all Tape commands will return Tape Status.
5115H
xx xx xx xx
5111H CO TS
XX XX
xx xx xx xx xx xx
40 00
00 00
00 00
00 00
5100H a) Correct Completion
5115H
xx XX
XX XX
5111H BE XX
XX XX
XX XX
XX XX
:?eX XX
XX XX
00 00
00 00
00 00
5100H b) Error Completion
Fig. 4-3 Configure Completion Status
4.3 DIRECT READ/WRITE
The Parameter Block for a Direct Read is shown in Fig. 4-5.
5115H 5115H
xx xx xx XX
j/xx xx XX XX
xx 'xx CO TS
00 00 00 00
"70 00 70 00
xx XX 20 00
20 00 20 00
XX xx 20 00
00 00 00 00
00 00 00 00
00 2C 00 2C
5100H 5100H
a) Before execution b) After execution Fig. 4-5 Tape Read
This Parameter Block instructs the TAPEMASTER to read the next re- cord on the tape, which has an expected length of 8192 bytes (2000H), and store it in system memory, starting at address 07000H.
After the TAPEMASTER completes the command and opens the Gate, the Parameter Block will have been updated as shown in Fig. 4-5b. Be-
sides the Status bytes, two entries have been updated. The Return Count field (05106-05107H) indicates that 2000H bytes were actually
transferred. The Records/Overrun field (0510A-0510BH) indicates that the block size on the tape was 2000H bytes, as expected.
The Parameter Block for a Tape Write command would be similar.
The Records/Overrun field is not used for Tape Write.
5.0 PARAMETER BLOCKS FOR l6-BIT SYSTEMS
Most of the examples presented in section 4 have assumed a Multi- bus system using an 8-bit data bus. Only minor changes to these examples are required so that they apply to a l6-bit host.
First, the Initialization must specify that the host has a l6-bit data bus, by setting byte l'of System Configuration Pointer to OIB.
This is shown in Fig. 3-2.
Secondly, in all Parameter Blocks requiring data transfer, the Width bit in the Control word should be set. This informs the TAPEMASTER that the logical width of the system bus is 16 bits.
The TAPEMASTER will automatically optimize the number of memory references by executing word (16-bit) reads and writes whenever possible. For example, if a read data buffer begins on odd ad-
dress, the TAPEMASTER will execute one byte read, and then continue with word reads.
If the Width bit is not set in the
~ontrolWord, the TAPEMASTER
will perform all byte operations.
6.0 OPTIONS
In the preceding examples, none of the Parameter Blocks used any of the TAPEMASTER options. This section covers their use. Most options are selected in the Control Word entry in the Parameter Block.
6.1 INTERRUPT S
As discussed in the TAPEMASTER Product Specification, the user may choose to have an interrupt generated at the completion of a com- mand. In general, non-vectored interrupts would be used for sin- gle-processor systems, or multi-processor systems in which inter- rupts are controlled by one processor. In multi-processor, posi- tion-independent systems, the Mailbox interrupt would be more use- fu 1 .
When a non-vectored Multibus interrupt is activated by the TAPE- MASTER, it will remain active until cleared by a subsequent com- mand. This is accomplished by setting the Channel Control Word
(at location 05020H in our example) to 09H, before issuing the Channel Attention for the next
co~and.6.2 LINK
The TAPEMASTER allows several commands to be executed in success- ion by linking them together. Linking and interrupts may not be used in the same Parameter Block--Link takes priority.
Fig 6-1 illustrates a Link operation. The Parameter Block of Fig 6-1a is an Erase command. Upon completion of this command,
the TAPEMASTER will check the "L" bit to see if another command
is linked. Since the "L" bit is set, it picks up a pointer from
Interrupt/Link (locations 05112H-05115H in this example), and exe-
cutes the Rewind Parameter Block at 06000H.
Sl15H 6115H
,
00 00
60 00 ) XX XX XX XX
XX xx XX XX
xx xx XX XX
xx xx XX XX
xx xx XX XX
xx xx XX XX
xx xx XX XX
00 40 00 00
00 00 00 00
00 50 00 34
5100H 6000H
(a)
ERASE (b) REWIND
Fig 6-1 Linking Commands
The Gate will not be opened between commands
tbut only after the
last command is completed
tor an unrecoverable error is detected.
6.3 BUS LOCK
When the TAPEMASTER transfers a byte or word of data to or from.
memory, it activates a DMA request, recieves a DMA grant, trans- fers the data, and then gives up the bus if necessary until the next transfer. If the Bus Lock option is selected, the TAPEMASTER will make only one DNffi request. When it recieves the DMA grant,
it maintains control of the Multibus until all its data has been . transferred, and then gives up the bus. The Bus Lock option elim- inates the handshaking between bytes.
6.4 CONTINUOUS TAPE
The Continuous Tape option applies only to the Cipher Microstreamer.
If this option is selected, the TAPEMASTER will cause the tape to continue moving after a Write command, in anticipation of another Write, avoiding the repositioning cycle. This will result in
longer than normal inter-record gaps (but still ANSI-compatible) and lower tape utilization. However, multiple record writes will be faster as the tape would normally reposition after each record.
The Continuous Tape option should only be used when a Write is being performed, and the following'tape is blank (such as during a disk dump operation).
Itis the responsibility of the user not to leave the tape moving after the last command.
6.5 WIDTH
Thw "W" bit in the Control Word indicates the logical width of the system bus (1=16 bits, 0=8 bits). In most cases this will be the same as the physical width selected during the Initialization.
The logical bus width cannot be larger than the physical width.
7.0 ERROR RECOVERY
This section outlines the procedures to be executed by the user to recover from various error conditions.
7.1 WRITE DATA ERROR
If a data error is detected by the drive during a read after write operation, it will notify the TAPEMASTER. The TAPEMASTER will in turn space back one record and attempt to rewrite the record. If the record cannot be written successfully after several retries, the TAPEMASTER will exit with an error code of OAH. The user should then execute a Space Reverse one record, erase a section of the tape using the Erase Fixed Length command, and attempt to rewrite the record.
7.2 READ DATA ERROR
If an error is detected during a Read command, the TAPEMASTER will automatically attempt several retries. If the record remains un- recoverabl-e, the TAPEMASTER wi 11 exi t wi th an error code of OAH.
The user may attempt more read
ope~ationsby spacing one record in reverse and attempting to read the record again.
7.3 WRITE TIME-OUT
A Time out error code (OFH) during a Write operation indicates that the TAPEMASTER did not recieve the expected number of write strobes from the drive. The TAPEMASTER will not automatically re- try in this situation. The user should rewrite the record "down tape" using the procedure of section 7.1.
7.4 READ TIMER-OUT
A Time out error code (OFH) during a Read operation indicates that the TAPEMASTER did not recieve the expected number of read strobes.
The TAPEMASTER will not automat,ically retry this situation. The user may attempt to read the record over by using the procedure of
section 7.2.
7.S OVERRUN
Overrun errors indicate a failure of the system to recieve or sup- ply data at the necessary rate. The user may retry after spacing
reverse one record.
7.6 BLANK TAPE READ
A Read on a blank tape will result in either a Blank Tape Error
(07H) or a Data Busy Time-out (OSH), depending upon the formatter
and the densi ty.
7.7 PARITY ERROR
A Parity Error (ODH) indicates that the data recieved by the TAPE- MASTER during a Read operation had incorrect parity. Recovery
should be as in section 7.2. The TAPEMASTER does not retry auto-
matically after a parity error.
8.0 COMMAND TEST
This section outlines the steps necessary to execute a brief TAPE- MASTER command test. It is not intended as a thorough test of all TAPEMASTER functions, but only as an example which may be easily
implemented by the user.
On the following pages is the 8080/8085 source code listing for the command test. This program is designed to run on an INTEL 80/
20 CPU board. With minor modifications, it may be run on any 8080 or 808S-based system.
The object code for the Command Test may be ordered from Computer
Products Corporation. It is available in PROM, magnetic tape, or
CP/M-compatible diskette.
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