2841 STORAGE CONTROL - STAr,E 2

(1)

N N

-

I 2211784

"ELD ENGINEERING DIAGRAM MANUAL FOR

2841 STORAGE CONTROL - STAr,E 2

MACHINE TY'E NUMBER, MODEL NUMBER (IF APPLICABl!) AND M~CHINE NAME CONSISTS 0' THE FOLLOWING:

Y26-4137-1

FORM NUMBER (BASE FEOMI* _____________ _ FORM NUMBER e FES 1*

*

NOTU

~ THE nDM AND ITS

n:s's

INClUOE A SYSTEM OATA FLOW DIAGRAM, UNI" "ATA AND CONTROL DIAGRA~. 1/0 OPERATION ~IAGRAMS. AND CONDENSED LOGIC FLOW CHARTS AS APPLICA8LE TO THE UNITeS) BEING SHIPPED.

m

WHEN A FEDM IS ORDERED FROM M~CHANICSBURG, ALL APPLICA8LE SUPPLEMENTS WILL 9E AUTOMATICALLY SUPPLIED. SU'PLEl4ENTS CAN IE ORDERED S[PARATElY BY APPLICABLE FORM NUMBER.

• 'IELD ENOINURING DIAGRAM MANUAL

**

FIELD ENGINEERING SUPPLEMENT

I_TEl.AliSUl 'Y:'IESS IAC.IIES CI.,.

^DAT[ ^{C ....}" 110. CRUll 110. 1I0ll

t-:::-::7"I'--:=-=·=-:-:--:-:~==----'-...;;..;~-u---+--,--::-~::-:-~-1t---+---il. "'lIT TO E ....

me.

110.

DIIlI

1 - - - 1 ....,

....,

!lAME FEOM 10 DWG D(sIG" MODILI DiiAll

eN'CI D .. -I

A".C

_._.

tclif el,

-

f - - -

J I

413343

---~~---+----

----

-

1 - - - 1 _

....,

1 - - - 1 :

~

~ I:

o

I N IJ' ...,

.

I

o

(2)

~@~ ~ Storage Control-Stage 2

Field Engineering

Maintenance Diagrams

SY26-4137-1

(3)

l?W~.

~ ~ ~ Field Engineering

Maintenance Diagrams

~@~ ~ Storage Control-Stage 2

SY26-4137-1

(4)

PREFACE

This manual contains flow charts, timing charts, and special- purpose diagrams to assist in the maintenance activity on the IBM 2841 Storage Control -Stage 2.

Simplified drawings have been prepared for functions which are not readily perceptible in the system diagrams, or for which the logic requires multiple pages.

The system diagrams at the engineering level of the equip- ment should be used in preference to the maintenance diagrams wherever there is a conflict between the two types of diagrams.

Second Edition

This edition (Form Y26-4137-1) is a merge reprint of form Y26-4137-0 and supplement Y26-060S.

Specifications contained herein are subject to change from time to time. Any such change will be reported in subsequent revisions or Field Engineering Supplements.

Copies of this and other IBM publications can be obtained through IBM Branch Offices.

A form is provided at the back of this publication for your comments.

This manual was prepared by the IBM Systems Development Division, Product Publications, Dept. 455, Bldg. 014, San Jose, California 95114.

ii (1/68)

(5)

Title

LEGEND . . . v

UNIT DATA AND CONTROL DIAGRAMS Storage Control and I/O Channel Interface . . .

1202

2311

Attachment Circuits . . .

1211

2321

and Optional Attention . . .

1221

Dual ehannel Seek Complete and Interrupt . . .

1222

2302/2303

Attachment Circuits . . .

1231

ERROR CHECK ANALYSIS DIAGRAM . . .

1301

I/O OPERATIONS DIAGRAMS Storage Control - ALU . . .

1401

2311

Seek . . .

1411

Write/Write A1I . . .

1421

2303

Attachment SiD - Write . . .

1422

2303

Attachment SiD - Read . . .

1423

Channel Data Transfer - Write· . . .

1426

SERDES - Read . . .

1431

SERDES - Read Address Mark . . .

1433

2303

Attachment SiD - Burst Check Data Flow . . . . . . .

1434

Channel Data Transfer - Read . . .

1436

Two Channel Interface - Part

1 . . . 1450-1

Two Channel Interface - Part

2 . . . 1450-2

Two Channel Interface - Part

3 . . . 1450-3

Two Channel Interface - Part

4 . . . . . . 1450-4

SIMPLIFIED LOGIC Serializer/Deserializer . . .

1501

FLOW CHARTS Storage Control - ALU . . .

1601

Reset . . .

1604

Initial Selection . . . .

1605

End Procedure - Part

1 . . . 1607-1

End Procedure - Part

2 . . . 1607-2

End Procedure - Part

3 . . . 1607-3

End Procedure - Part

4 . . . 1607-4

End Procedure - Part

5 . . • • . . . 1607-5

Date

(7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (10/67) (10/67) (10/67) (10/67) (7/67) (7/67) (10/67) (10/67) (10/67) (10/67) (10/67) (10/67) (10/67)

CONTENTS Title . End Procedure - Part

6 . . . 1607-6

End Procedure - Part

7 . . . • . . . 1607-7 2311

Seek . . .

1612

2321

Seek . . .

1613

2303

Seek . . .

1614

Write . . .

1621

2303

Write . . .

1622

Write Address Mark . . .

1623

2303

Write Address Mark . . .

1624

Channel Data Transfer - Write . . .

1626

Read . . .

1631

2311

Read . . .

1632

Read Address Mark . . .

1633

2303

Read . . .

1634

2302

Bead Address Mark . . .

1635

Channel Data Transfer - Read . . .

1636

Microprogram Logic . . .

1691

Dual Channel Microprogram . . .

1692

TIMING CHARTS Reset . . .

1701

Start-Stop Timing . . .

1702

T. R.

O.

S. Scan . . .

1703

Storage Control - ALU . . . • . .

1704

2311

Seek . . . • .

1711

2321

Seek . . .

1712

Write . . .

1721

2303

Attachment SID Write . . .

1722

Write Address Mark . . .

1723

Channel Transfer - Write . . .

1725

Read . . .

1731

Read Address Mark (Page

1

of

3) . . . 1733

Read Address Mark (Page

2

of

3) . . . • . . 1733

Read Address Mark (Page

3

of

3) . . . 1733

2303

Attachment SID Read AM (Page

1

of

2) .. 1734

2303

Attachment SID Read AM (Page

2

of

2) .. 1734

Channel Data Transfer - Read . . .

1735

2302 - 2311

Track Format . . .

1736

2321

Track Format . . .

1737

2303

TracK Format . . . • .

1738

Date

(10/67) (10/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (10/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (10/67)

(7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67) (7/67)

2841

Stage

2

FEMDM

(10/67) iii

(6)

This page intentionally left blank.

iv (1O/67)

(7)

In positive logic representation, signal levels are disregarded. The negator (N block symbol) is used to invert logic, not level. Passive elements (such as drivers and pulse shapers) generally are not shown, since they contribute nothing to the logic.

LOGICAL ELEMENTS

f l

AND

E-

Exclusive-OR

PASSIVE ELEMENTS SPD

-G-

Sample-Pulse Driver

STORAGE ELEMENTS

E-

OR

-8-

NOT (Negator)

Schmitt Trigger

AC

123~AID Page

REGISTERS AND COUNTERS

Partial ~

Transfer ~

Clear 0 3

Full

Transfe~

TIMING ELEMENTS 2.Sms

-G-

Single-Shot

10 kHz

-B-

Flip-Flop (Complement Input)

Oscillator

Differential Amplifiers

FL

Flip-Latch

LEGEND

SWITCHES Name

0- FS=

Momentary

: SW :

Name

^I ^I

Er

Multi-Position

^~

Single-Throw

xx Abbreviations

--B-

^V

⁼

Voltage Amplifier

LD

=

Line Driver

R X

L T

=

Line Terminator MD= Magnet Driver Single-Ended HD= Head Driver

Amplifiers ID = Indicator Driver CD

=

Core Driver

Data Control Clear

Polarity Hold

I l£~counter

^Advance

Gate~ ~ + For UP Count

I ⁺ ¹ ^-

For DOWN Count

Clear ... - - - . - - -...

i I~cator

(Reset) , . . - - - -. . Register Name ---_·I ... ^~

o ^AA123

Logic

/

High Order

Page Number

MI SC ELLAN EOU S

Parity Check on Data Flow

Parity Generator

Number of lines

in Bus

15 12 115 Gate--1<

I

Indi.catable Bus

--~ ^{. .} pC-·~·-16-- ^... ~~- ^{. .} ~-

Full-Time Pluggable or Switchable

<:.arry

Multiple Line Transfer

1 2 3

2 3

Counter

o 8C321

High Order

On-Page Connectors With Alphameric

Locations

7 -0 0-

B4 A3

~

With line-of s~

Off-Page Connector

114093 B

I

2841 Stage 2 FEMDM (10/67) v

(8)

~ o

~

=-

o

.,.

-

=t

o c:

=-

o

.,.

2

47 47

-I

~

.,.

0 0 o

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C HAt"-IEL TAGS OUT

~ I I I t n i E ^lIIt > en'"

;

^{;j~~~ ~~}

~ n i g ! : l : ~2

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~

§ §

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^{GB 061}

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³

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^ADDRESSCOMPARE

I

GB081

r--t i •

SELECTION GBIOI

GA043 3 GB041

I ELEC~O~UT

CH8 ...

7 _-+_-+-_

~S~E~R~V~IC~E~~~OU~T __________ -+-4 __ ~ COMMAND OUT

5 0

6

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^OUT ^•

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CARRY OUT -

r:1

^>

DHOII CH FILE ENT 0 7 1 ; 3

~

_ 1CAS II ONLY)

CL FI LE ENT ST ASHB

1

CL 0

_ Iln !1P

I

DS II

s

CHANNEL TAGS IN

i n

I ,..

I!

.,.

READ LATCH

1 n

WRIT~H .,...J.P-OL-L~L..

SERVICE IN CTR

· rr

~ QUEUED

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P GBI41

r-

^GBI61 _...._{_+-_~--Ir}_{IG GATE}

L-J ~ ~

DO Dzi DJD41D6 DI 05 D7 L GBI61

» -< 1 GBI31 GBI61 GB081 GB161 1 P

~ ~

_,... I

IG REGISTER

1

~ Z -t

\AI o

N 0

... Z W N N

N W

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15

7

1

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GB201

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All 01-14 I

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B REG SOU"CE DECODE

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7 u§

DLO II ~~~UU-:.m; RIIII~---

J.-, J., r1 ^J., ~ ~ ^{J., J.,} ^ret-, ^ret-, i

LfJ ., qu I ^L1fJ lf1 Y Lf1 LfJ qu YJ ^~

~

¹⁹¹⁷⁵

~

DBOOI A REG SOURCE

DECODE DA01I-041 BRANCH OECODE

DLOOI-OII

CB

r----II~D VOO 1 I

LrPcl

^ADDRESS

r-USPI21

[ j

BRANCH DECODE

1.1

_-I

^DHOOI-OII

lJ::l

^SENSE

l6

ALU BYPASS (YBY)

I~~~

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42

I

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o

RSOOI· ^ST

Ii

MN

P OP

LI

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PRDD!J'I~1

_~ IPRDW0021l1 ₁ IP UR _RUDOI

l rP:l1

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~

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^{IP DL}_{1 ROOII}^7. ^{IP FR.}_RFOOI

^I'll _I

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I

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~I~ ~~LTJ ~----~I ^{ ----__} ~

~ i ^~ ; __

C_L_F"7' L_E_ENT_--II--_ _ _ ,

~ $ ^I

MAN OR FEAT ENTRy!

^,

BAl21

I

A REG ER IE IH ASHB BA091,IOI,III

~=-o~

~

=-

(CAS II ONLY)

~ I

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r

ISINTERFACE,J

~

g 1

^HBI51 ^BAI31 ¹

...--+---.. r--~~~~-L~ ~ JX:A

I

B REG ASSEMBLER

I

BBOOI-OII

I

A REG ASSEMBLER

BAOOI-OBI ~

L..-"5========-I1 CL

(X)

+

"U

ALU ERROR 130 - -

H

~C-A-R-RY-A-ND--I

Iz6 ~ ^g :~g:~~E:~

1²⁴ ^- ^YCV^0*

SERIALIZER/ CH FILE ENT 3j5f 67

1

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OESER IAL I ZER x

.... _Z.::,.3_11_-_Z.::,.30_Z_-_S_00...,:3_1-+ __ -t PC

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g ~

_~

2303-HCOOO ST I ,.. - 0 - N - - ~

- -

....

en

, L!..

I

^{A REG. 1}^B+P --r---:-A:-:'LU~F---.--..L-- RAOOI

'I

^{r - - -}

^I

^BYPASSI ^t ^P

I ^ALU ^{BIT 46}

t .J

^PARITY I

1

~ _________ ...!C~O:!J.M!...!PL::..!:E:.!..!M~EN!.!.T!..---4 ____ " RBOO 1-002 ~ 6 r-- CIt ~ .... ~~ ~ ~ ~

", L-r_2 ... 3;,;,.2....;,1-r--S D ... 0..:.3...,...~ ~ ^:

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l: - ~ ~ ~

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0 BUS DECODE

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w ....

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PART IAL SUM T /C

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^{PG I}^...

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^_P_ _ _ _ _

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RBOOI-002

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' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - J A L071 AL20 I

' - -

-

110--,

I

⁰

1'--__ ....:Y~C..:.:.N

^...5<__ __________________

_I~

^...^{IOVOO 1}

~

-t

~""!~E~: ~,.. ~~

~ :><: : ~ ~ ^• OPTIONAL ~

~ > -I I ffTERFACE

g

~>

OPTIONAL INTERFACE

STORAGE COffTROL AND I/O CHANNEL IffTERFACE

STORAGE CONTROL AND I/O CHANNEL INTERFACE UNIT DATA & CTRL OIAG DATE

Z84IR

IBM ¹²⁰²

UNIT DATA AND CONTROL DIAGRAM - Storage Control and I/O Interface

A

B

c

o

E

(9)

(10)

I ² I ³ .. ₁ ⁵ 1 ⁶ I ⁷

REFER TO PAGES FA021, 022, 023 A ENTRY

FOR INTERFACE INPUT & OUTPUT LI NES

~~

ACC & MOD 0 A3B4BI2 , FAIL USE ALT

A

MOD MOD I A3B4DI2 ... , SAFE

FILE SAFE ( IS 2)

ENCODE LOGIC

MOD 2 A3B4DII .~ ^CAI5

A

FROM UR

..

MOD 3 A3B4B09 J DR I VE SELECT ... BA 131

REG

....

(I LINE PER DRIVE)

....

MOD 4 A3B4B03 HBI31

MOD 5 A3B4B02 ) MOD 6 A3B4B04 ~

HB071 MOD 7 A3B4B05 J DRIVE READY A3C5B03

FSO F ^~

HB081 ⁾ DRIVE OPERATIVE A3C5B02 I AlT CA13 A

" D" BUS ,~

~

DESTINATION IS FT REG CDl3-D BUS

~

C2J5Bl0 SERIAL WRITE DATA (SD271)

..

²³²¹^FILE READ SAFETY A3C5B05 ^FSIFS2 E ^L ^(STATUS)

RD021

..

WR I TE SAFETY A3C5B 12 FS3 HB091 FT 5 OR 6 HBI41

HBI42

A FT FTO A3G4BIO ((CONTROL) STR I P READY A3D2BI2

REG

A3G4D11 'CELL ADDR

FS4 S

B

FT1 SET

..

I NVAL I D ADDRESS A3E5D02 T

....

^FS5 _A

CDI3 FT2 A3G4DI2 HEAD ADDR SET

...

AUTO RESTORE A3D2B02 _FS6 _T

HBOOI FT3 A3G4B13 FINGER ADDR SET

.. ..

CE CELL LOCATED A3E5BI2 FS7 U

CNS

...

^FT4 ^A3H2BOS HEAD POS ADDR SET

... ..

S

NOT 2311 SEL

...

FTS A3H2D04 SUBCELL ADDR SET

..

.. ^..

USABLE AREA A3ESB02

..

...

_FT6 _A3H2D09

..

^.... ^I--

~ EARLY INDEX A3D2BOS

..

("D" BUS S OR 6 FT7 A3KSD09

J 2321 ON LINE A3D2B03

...

0

..

^r ^{I E GATE} A

J

....

_HBOOI )

FT S OR 6 CNTL I E6-2321 CA 14

I FT 5 OR 6 HBI51 BA III A

FTO ASM

(- AM

..

^0-1-2

C

... _CONTROL _A3A3D12 PROCESS TIME

.. ....

FC7

...

rMOD 0 ATTN A3C2D04

I SEEK A

..

) TO PAGE HADOI

~ MOD I ATTN 0-3 .. ENTRY

...

HB021 A3C2D07 COMP HA 121

~ MOD 2 ATTN A3CSD04 GATING

....

^0-3

~

COlq-D BUS

~

A3F4B05 (SC)

DESTINATION IS FC REG FC -FCO WRITE GATE ,',

..

MOD 3 ATTN A3C5D07 I--

RD021 REG -FC1 A3F4B03 MACH RESET ,'(

:-

(ATTN RES) ^rMOD 4 ATTN A3 ESD04 ~-II ..

..

^A

A -FC2 A3F4D06 SEEK START

* ..

_~MOD S ATTN A3ESD07

....

_HBI41 .... _ASM

...

3-4-S

..

_~MOD 6 ATTN

+

-FC3 A3F4DD4

,.

,', = GATED BY FTO A3D2D04

CDI4 -Fc4 A3F4B04 JR STA ,', (CONTROL)

..

^~MOD 7 ATTN A3D2D07

HBOII

-FC5 A3F4D02 HD SEL >'<-

..

^HBIOI

4

^A

⁰

.. ..

CNS

..

^-FC6 A3F4D07 REST. ,', ....

..

ENTRY ^4-7

....

_HAI31

FT S OR 6

....

-FC7 A3F4B02

...

..

^r

...

_HBOl1 J CELL ,MOD 8 ATTN A3B3D04 0

I

PAR ITY BIT ~ MOD 9 ATTN ADD'TL

12-IS ...

-FCP A3J4B2

_{- - -}

A3B3D07 2302 _HB142

...

^A

~MOD 10 ATTN A3BSD04

... ^...

_ASM ^I--

HEAD

ADR REG

f

MOD II ATTN A3B5D07

t

^6-7

(OLD HD

...

^DATA ^A3C6DI2 rMOD 12 ATTN A3B5DI2

FROM

ADDRESS A LI NE A3C6B 12 ~ MOD 13 ATTN A3B5B05 USE AL T HAI41

FC REG ~ _STORAGE)

-

~ ^DVRS ~ MOD NOT INH I BII ^A

r - HB141

..

^A3c6ol1 14 ATTN A3B5B02

- ^E

HB142 FRO~ ^A3C6B09 ~ MOD IS ATTN A3B5B03 CA 12

...

FT2 HB041

A3C6B03 SERIAL RD DATA ...

C2E~B02

^HBI06

c

.. ..

^SEEK

J

...

_HB031

_... ^.... ...

_A3C6B02 _ADDRESSES

...

..

^A3C6B04

(FROM FC7

...

A3C6BOS

...

FT 5 OR S ^A ⁾

..

_HB042 2321. AND OPTIONAL ATTENTION

ALT CAI4

-

GATE ADR REG BYTE

DATE

I I

HBI31

NOTES;

I

^TYPE

^I

^2841R

I. ALL SCOPING POINTS, EXCEPT READ & WRITE DATA, ARE ON 2841 A3 PANEL AND ARE NOT NECESSARILY

11M ¹²²¹

DIRECTLY ON REGISTER OR BUS LINE AS INDICATED BY THIS DIAGRAM.

UNIT DATA AND CONTROL DIAGRAM - 2321 and Optional Attention

(11)

I ² Î ³ Î Ît 1 ⁵ 1 ⁶ Î ⁷

WIO DUAL

2311 ANY CHANNEL

A

.... - _-

ATTN ATTN JUMPER ,.

~ I NTERRUPT A

OUT

- ..

~

-

^~

HA091 HAIII

CHNL SW TO A SELECT

SWITCH

Wlo DUAL CHANNEL SW TO B

B

GB091

ADD'NL ₂₃₀₂

- ^..

^ANY_ATTN ^{CHAN A}TAGS ,It

r

OPT

I - - QUEUED

-

^CHNL

IGG LATCH

..

_INTPP _~

..

CTRL

-

POLL ENABLE

.

^A.;i3

HBI16

.

_HBI11 _GBI61 ^,.

_.

INTERRUPT B

~ GB236 ^~

C

A ENTRY (SEEK COMPLETE)

jl'

OPT 0-3

-

^UNIT ^ATTN ^{S.C. AND}

ATTN ^.#' ATTN 0-3 CHNL

0-3 REG ~

0-3 ASH

-

~ GROO6 ^~ BA206

GROl6 BA216

HB10J GB246 GR026 BA226

GR036 BA236

0

4-7

..

_ATTNUNIT ATTN _4-7 S.C. AND ^~

4-7 CHNL

REG

GR046

..

^ASM

BA246

4-7 GR056 BA256

~ GR066 BA266

..

_GB247 _GR076

E

BA276

DPAL CHANNEL SEEK COMPLETE AND INTERRUPT

DATil

I

1

^TYPI

I

284IR

UNIT DATA AND CONTROL DIAGRAM - Dual Channel Seek Complete and Interrupt

11M 1222

(12)

(13)

...

V>

o ...

...

V>

o ...

I ² I

I~

TROS SAL.

OUTPUT LINES ODD BIT

1⁴7

OEOOI I

TROS SAL. 1 0

I ³⁸

OUTPUT

LI NES \40 EVEN BIT _I

DEOII 142 I

TROS ADOR

I

^P

X REG I

•

⁰

KK321 7 TROS ADDR

I

^P

W REG

I

• I:

KKOll

BUS OUT

I:

LI NE RCVRS

GA031

DR REG

I

^P

•

I ⁰

RD041 7

ERROR CHECK ANALYSIS DIAGRAM

J I ^It

YCH, YCl, YCA, YCB, YCK YPA

I

YPS

YCN, YPN, YCD, YCV, YCC, YCS YPC

0 FILE

DATA

o I

REG PAR/SER

7

I

^{WR ITE}

5D141 DATA

7 5D142

o I

7

I

^SD151

BIT RING

SD131 SD132

I s _I 6 I ⁷

I ^SENSE

ÂH' ÊRROR ÎNDICATOR ^liND

I

LATCH DR IVER

I ^A

PAR lTV I CHK

;

^SPill SENSE AMP

SPI21 SPI41 SPI41

I

J

ERROR INDICATOR

I

^INO

I

^~

I

^{CONT REG} CONT REG MRITY

PAR lTV LATCH DRIVER

I ^CHK CN PARI TY

I

I CONT REG

SPI31 SPl41 S.P141

I

8

PA ADDRESS ERROR INDICATOR

I' N' I

CHK LATCH DRIVER

PX

PW ADDRESS

SP121 SP141 SPI41

I""-

ALU

SUM P BIT ERROR

NOT SUM P BIT

A REG P BIT AL211

C

NOT A REG P BIT

4 I

I

ER REG INDICATOR

I'N' I

BUS OUT I

PARITY DRIVER

CHK 2 J

• ^-

I _DATA

GB121

o I

^REOOI ^SP141

I

0

BP WRITE DATA

ONE CONVERS I ^(}I INHIBIT I NO I CATOR

lIN' I

I r

^CHK⁵⁰¹⁷¹ ^CONTROL ^DRIVER

4 POS MACHINE STOP

-

B I NARY

SPIOI

-

^COUNTER ^SP141

NOT ONE 5D201

CE AID INDICATOR

E

DRIVER

I ^IN, I

REOOI SP141 PROBE

ERROR CHECKANAlVSIS DIAGRAM

DATE

I I

I

^TYPE

I

^2841R

18r., ¹³⁰¹

(14)

...

tI>-

o ...

I ² ³ I

DE011 YCC BITS .-

L

BY YCV 0

*

COMPLEMENT REGISTER

I

RB021 ^~

..

^{PART IAL}

RB022

': _... .. ...

^{SUM 0-3}

---.

DR RBOOI

REGISTER

• ..

^{PART IAL}

RD041

... .. _...

^{SUM 4-7}

.. ..

.-.

^RB002

YCK 0-7

A

DEOOI 0-7

..

REG ISTER

...

A INPUT

A _{f - - -} RAOOI

BUS ASMB BAOII BA081

C C FI ElD 3 BITS BIT 0 BIT I BIT 2

0 0 a ADD OPR - NO FORCED CAR IN - NO CAR OUT TO ST3 0 0 I ADD aPR - FORCE CAR IN - NO CAR OUT TO ST3

0 I 0 AND OPERATION

0 I 1 OR 0 PERA TI ON

I 0 0 ADD OPR - NO FORCED CAR IN - LAT CAR OUT TO ST3 I 0 I ADD OPR - FORCE CAR IN - LAT CAR OUT TO 5T3 I I 0 ADD OPR - ADD IN ST3 - LATCH CARRY OUT TO ST3

I 1 1 EXCLUSIVE OR

/0 OPERATIONS DIAGRAM - Storage Control - ALU

" ^I

.. _...

^FUNCTION

DECODE CARRY IN

DECODE AL081

AND AL091

LATCH

» r

AL21! ^r₀

I ^I

^{CARRY IN} ~ ("")

» NOT CARRY IN ^'70^'70-<

" " "

.. ...

ALU

... ...

ALOOI - AL071

~~

AlU CO NTROl liNES AND "Amr A7mf ^A/OR

ADD OFF ON ON OFF

EXCLUS I VE OR OFF ON ON OFF

AND ON OFF OFF ON

OR OFF ON OFF ON

5 6 I ⁷

CARRY OUT TO ST3

... ...

RSOII

SUM P BIT

--..

^ALU

_A

NOT SUM P BIT

...

_ERROR ALU ERROR 110...

...

REOOI

-

A REG P BIT ...

...

» z 0 z NOT A REG P BIT

1:1 -I AL211

0 »

'70 z

0

-

DATA SWITCH

"

~ SPI51 _--... _{D BUS}

B

.. ... _...

^POWER

.. ^...

^{D BUS}

~ ... ..

A TO D

..

XFER

.. _....

ALIOI

OR

....

_{AL 141}

-

ENTER ALIOI SP061 ~

- ENTER ~,

0-7 SUM

.. ...

_OUTPUTSALU

^... ...

D EQUAL ZERO

C

BIT ZERO CARRY

--.. ... ....

_~ SUM P BIT

...

CARRY OUT NOT INH I BIT 3 _A SET ALU

--.. ...

AL201

OUTPUT _~

B3 CLOCK 3

AL ]l·11

0

ALU D POWER BIT N

ALXXX ALYYY

m'R'V CARRY

0 ALOOI ALlOI

OFF ON I ALOII All II

2 AL021 ALII I ^~

ON OFF

3 AL031 ALl21

4 AL041 ALl21

ON OFF

ALl31

5 ^AL051

6 AL061 ALl31

E

ON OFF

7 AL071 AL141

1/0 OPERATIONS DIAGRAM STORAGE CONTROL ALU

DATIl

I

1 ^,nl

^12841R

11M 1401

(15)

...

II'>

...

I ² I

- UR REG 0 BIT

---

^RUODI

- UR REG I BIT

---

^RUDDI

- UR REG 2 BIT

---

^RUDDI

- UR REG 3 BIT

---

^RUDDI

- UR REG 4 BIT

---

^RUDDI

- UR REG 5 BIT

---

^RUDOI

- UR REG 6 BIT

---

^RUOOI

- UR REG 7 BIT

---

^RUOOI

+ DEST. IS FT - - - RD031

+ D BUS OBIT

---

^ALIDI

+ D BUS I BIT

- - -

^ALlII

+ D BUS 2 BIT

---

^ALlll

+ D BUS 3 BIT

- - -

^ALl21

+ D BUS 4 BIT

---

^ALl21

+ D BUS 5 BIT

---

^ALl31

+ D BUS 6 BIT

- - -

^ALl31

+ D BUS ? BIT

- - -

^ALI41

+ DEST. IS FC

- - -

^RD031

+ CN5 B IT LATCHED - - - DVOOI

-Q CYLINDER ADDR REG 128 - FAD 11 -Q. CYLINDER ADDR REG 64 - FADi I -Q CYLINDER ADDR REG 32 - FADII -Q CYLINDER ADDR REG 16 - FAOII -Q CYLINDER ADDR REG 8 - FADII -Q CYLINDER ADDR REG 4 - FADII -Q. CYLINDER ADDR REG 2 - FAOII -Q CYLINDER ADDR REG I - FADII

+ CA 14 DECODE

- - -

^DA041

+ USE ALT CA DECODER PI- DADOI -Q SEL SEEK INCOMPLETE--- FADI I -Q SEL ON LINE FAOI I

-Q FILE UNSAFE FADII

-Q SEL END OF CYL

- -

^FAOII

-Q SEL FILE READY

- -

^{FADI I}

I/O OPERA TIONS DIAGRAM - 2311 Seek

3 It

FT REG

- -

-

+ r - - - HADDI

FC REG

L....-

HAOII

-Q OA 128 +

2311 _-QOA 64 2311 +

INTERFACE

32 LINE

-Q OA +

ENTER

-Q OA 16 RECEIVERS

+

-Q OA 8 +

-Q OA 4 +

-Q OA 2 +

HAD51 ^-QOA I

HADll ⁺

2311 2311 + ₊

INTERFACE LINE ₊

ENTER RECEIVERS

+

HA051 HA081 ⁺

I s _I 6 1 ¹

FADII -Q MOD 0 SELECT

2311 2311

MOD INTERFACE FAD II -Q M()D I SELECT

SELECT EX IT FADII -Q MOD 2 SELECT

FADII -Q. MOD 3 SELECT

A

FAD 11 -Q. MOD 4 SELECT FAOII -Q MOD 5 SELECT FAOII -Q. MOD 6 SELECT

HA041 FAOII -Q. MOD 7 SELECT

-

^HAD31

-

2311 FT REG 0 BIT -Q. CONTROL

2311 2311 TAG 2311 FAD I I -Q. CDNTROL

FT REG I BIT _Q SET CYL

2311 FTREG 2 BIT LINE DRVRS _-QSET SIGN &. HEAD INTERFACE FADII -Q SET CYLINDER

EXIT FADII -Q SET HEAD & 0 I FFERENCE

2311 FT REG 3 BIT -Q SET DIFF FADII -Q SET DIFFERENCE

B

HA021 HA041

2311 SELECTED 2311 SELECTED

I

_~

2311 BUS 231 I FAD 11 -Q. FILE BUS 0

DRIVERS INTERFACE FAOII -Q. FILE BUS I

EX IT FAD I I -Q FILE BUS 2

FAD I 1 -Q. FILE BUS ₃ FAD I I -Q. FILE BUS

4

FAD 1 I -Q FILE BUS 5

C

FAD I 1 -Q. FILE BUS 6

HA021 HA041

I

^{FAD 1 I} ^-QFILE BUS 7

- ~

~

HAI41

0 OA 128

IC INPUT BAOII - FILE ENTRY 0 BIT OA 64

TO A REG BAD21 - FILE ENTRY I BIT

OA 32

16 ASSEMBLER BAD31 - FILE ENTRY 2 BIT

OA BA041 - FILE ENTRY 3 BIT

OA 8

4 BAD51 - FILE ENTRY 4 BIT

-

OA

OA 2 BA061 BAO?I - FILE ENTRY 5 BIT - FILE ENTRY 6 BIT

OA I

BAD81 - FILE ENTRY 7 BIT

-

^HAI21

_£

HAI31 HAI41 SELECTED SEEK INC

SELECTED ON LINE BAI31 + 2311 OPERABLE

SELECTED UNSAFE SELECTED END OF CYL

SELECTED READY HA091 I/D OPERATIDNS DIAGRAM

2311 SEEK

DATE

I I

I

^rYPE

I

2841R

IBM ¹⁴¹¹

(16)

I ² J

OPTIONAL FILE SEL.

2311 MOD N SELECTED DR REG BITS 0-7

HB081

HB061 RD041

0':875 KC 2.5 MC OSC

SD181'

WRITE GATE (M ICROPROGRAM CONTROL) HA 071

ADDRESS MARK (MICROPROGRAM CONTROL) HA 001

DR REG BIT P RO 041

* :

2321 REFERENCE

I/O OPERA TIONS DIAGRAM - Write/Write AM

3 I

1

0

I

^FILE^DATA

7 REGISTER SET FOR

FOR RESET SDI41 SD142

BIT RING ADV BIT A RING ADV BIT

SELECTED PHASE X

WRITE OSC

J..---...

WRITE PHASE Y

TRIGGERS RING RING

DRIVE

SD181 SD121

SD131 SD132

WRITE CLOCK GATE

5D091

5 I ⁶ ^I ⁷

A

H

⁷ ⁷ CONVERSION ^PAR/5ER SER OUTPUT DATA ^{r - - -}^A DATA

WR I TE TR G 5 D 18 I B I T5 10-

0

~'l

7 SD151

RS 0 2 1 - - BIT RING 0 (ST 4)

B

FDR SET

J

0

~ I:

1 .... _~ _FILE

HOD 0-7 WRITE DATA

& RESET I - - ^WRITE WRITE

2 CLOCK DBl FREQ DATA

3 & DATA WR DATA DRIVERS

4

I

MOD 0-7 WRITE DATA

~

^~^SD181 ^5D161 OPTIONAL FILES

'"'"""

7 WR ITE GATE

I~ 7 ^.... ^SD111 ^,'rSD166

~

0 ^INHIBIT

INHIBIT CLOCK WR ~

~ CLOCK NOT

~ WRITE

c

(C LOC K B I T5)

L NOT WRITE TRIGGER 5D181.

~ J L . . . . - -

SD151

L

^COUNTER COUNTER 1

COUNTER DRIVE 4 POS NOT COUNTER 1 WR DATA

DRIVE BINARY !(DNVERSION

COUNTER CHECK

RE 001 - - SER IAL WR ITE DATA ERROR

o

COUNTER RESET

SD191 5D201

f

^5D171

I/O OPERATIONS DIAGRAM WRITEjWRITE AM

DATE

I I

TYPE j2841R

II", ¹⁴²¹

(17)

2 3

CLOCK TRACK ClK TRK 50 NSEC DlY

(FROM SELECTED 2303) PHASE ZERO

ClK TRK 120 NSEC DlY

PHASE ONE TO

r-______

~C~l_K_T~R_K~18~5~N~S~EC~D~l~Y __ ~r_--~--~L_LJ

ClK TRK 200 NSEC DlY ClK TRK 2 0 NSEC DlY ClK TRK 20 NSEC DlY HCOOI

BIT RING DRIVE PHASE ZERO J __ DELTA BIT RING

DELTA BIT RING WR CLOCK GATE ^N DRIVE BIT RING 7

-

HC 161

BIT RING 1

-JA _- _----

^FL

BIT RING 2

60

PHASE TWO

PHASE THREE

PHASE FOUR

~I'HASE

^FIVE

HC 131

BIT RING BIT RING 0

Fl

- ---

BIT RING 2

. ..

I

BIT RING 3 ..

NOT PHASE THREE PHASE FOUR BIT RING SEVEN NOT WRITE AM WR ITE GATE

5

BIT RING

°

..::B;..=U~F.:....F E?'R.:...::B ... I.!...T -'0'--__ -1 A BIT RING I

~B~U~F_F~ER~B_I_T ____ ---1 A BIT RING 2

~F~R .... 2~ ________ -i A

BIT RING 3

FOR 3 ^A

BIT RING 4

FOR 4 A

"':B"71 "::'T-:R~I~N:':'G-5:---t

FOR 5 A

-B~I ~T"':R;"'I-N-G-6-::---t

~F~D~R~6~ ________ -IA BIT RING 7

FOR 7 A

OR

HC061

PHASE THREE WRITE DATA NOT WR AM

TO DR GATING HC211

NOT FDR P HC071

~---~ A WRITE DATA SAMPLE

~--r---+---~~OR r---;::F~DR::-::P~--1 A WR ITE FF

FT 0 FC 7

WRITE PHASE DATA FF

~~7:IT~S~~~1 ~:7:~~E':::O---rA~A11---L...IIl...H-C-07-1-.J ~

^_

~~

^_

DR REG 0

BUFFER REGISTER

HC 171 DR REG 2 DR REG 3 DR REG 4

I' I r---

----

FL

---- ----

FL

FOR 0 ..

FOR I •

..

FDR 2 ...

FDR 3 ..

FOR 4 ..

FL Fl .. WRITE GATE _

]A

~RITE NOT WR CK GATO START

po

FL AM BIT

MISSING

NOT AM GOOD 1 A

L

SEARCH NA, 1

I

-

HCI61 1600NS

----

BIT RING 3

BIT RING 4

----

Fl

----

BI T RI NG 4 ..

----

Fl

A5 BIT RING ~

~A -- ----

^Fl

^..

SET FOR

----

50201 DR REG 5 FOR 5 ..

WR ITE GATE ... RESET FOR Fl

~PH7:A;;;::S~E-:-:o~m~E

:;:--,1

1 A

I

BIT RING 0

-

_HC091 OR REG 6

^----

FDR 6 ..

FL

----

WR GATE

JsSI v~~

~~ ~ B~I~T_R~IN~G~5~

__

~==+=~==I---~~6~6~

__

4=~::=f==I---~B~I~T~R~I~N~G~6~,~~

50091

1T ^~

^_:L__

^~ ^_~L__

^- DR REG 7 FDR 7 ..

FL

...

HCI61 BUIITJRUI~N£GJ6~ __ ~::t==f==I---~~A~7~ __ +=~::=f==I---¥BUIITJR~I~N~G~7y"~

Lt ^_F~__ ^~ ^_~l__

^r

DELTA BIT RING RESET BIT RING RESET I/O OPERA TrONS DIAGRAM - 2303 Attachment SID - Write

He221 HC231 He221 HC231

----

DR REG P FOR P •

.PO

----

FL

6

DBl

BIT RING 0 NOT ADDRESS NOT WRITE GATE

WRITE DATA ERROR (ER REG BIT I

WR I TE GATE

DELTA BIT RING 7 WR ITE CLOCK GATE

RESET ST 4 VFO RESET

A

I - -

OR

1

OPT MOD X WR DATA (TO DEVICES)

MOD X WRITE DATA

SD161

WR AM FL

HC051

FL

SD091

FL

- ---

HCIOI

WR I TE GATE

WR CLOCK GATE

2303 DATA TRANSFERRED

(SET ST 4)

..

po

2303 ATTACH SiD WRITE

DATE

IB~ ¹⁴²²

A

8 c

o

E

(18)

(19)

I z I

⁾

I , _I s _I ₆ 1 ⁷

A

+0 BUS 0 BIT ALlO1 WRITE SVC SVC IN

LA TCH _{" -} _r-- REQUEST LATCH

r-H

LATCH

r--- RESET A TIME

I

^GB131 ^,..- ^A ^GB141

^-

^GB141 ^~

RDO~l DEST. IG

A KCO~1 C3 D TIME

+ C3 A TIME

8

+CA 15 DECODE

--

00'041 ^TRF +SET D TIME " - - - TRF RESETS

+uS E NORM L CA

-

DAOOI ONE TWO i . . . . -

GB061 ^~

+SET D TIME

-

- SVC REQUEST

-RESET C TIME GB131 -RESET B TIME GB131 ^{r - - - -} GB1Sl

C

+SERVICE OUT CTI

-

^GB061 ^to-

SVC IN

RESET 1

0

_READ LATCH

--

^GB131 ₊_{A TIME}

GB1Sl

~

+CA 13 DECODE

--

^DAo4l _{RESET 2}^{SVC IN}

+USE NORMAL CA

--

^DAOOI

+C3 A TIME

--

^KelOl _GB15l

E

OPERA T IONS D JACM"

CHANNEL DATA TRANSFER - WR J TE

DATIl

1 1 '''I

^j2841A

OM ¹⁴²⁶

-

I/O OPERATIONS DIAGRAM Channel Data Tr nasfer - Write

(20)

l ² I ³ I ⁴ 1 ⁵ ^I ⁶ ^I

⁷

A

RS 021 ---- BIT RING 0 (ST 4)

J

^~

VFO ose PHASE X BIT RING ADV RD 041 _ _ GATE FOR TO DR REG

PtV'.SE BIT BIT

--

^{FOR SET}

r-- PHASE Y ^RING DELTA RING ADV 1

-..

GENERATION DRIVE RING 2 ^&RESET

3

If

8

5 ^{SET FOR}

50131 6

50181 50121 50132 7

-

⁵⁰¹¹¹ FOR RESET

....

J -

--- L

^FILE

r - -

VFO eTl

READ GATE HA091 DATA

(BROUGHT UP BY "PROG)

-

^REGISTER

C

RD 041 ---- DR REG BITS 0-7 50091

50141 50142

-

SEPARATED DATA

-

L ^- l

DELAYEO DATA ---- SO 061 DATA DATA READ

-{,so066

t

SEPARATION DATA GAP

-

DATA GOOD READ CLOCK GATE

& eTl GOOD CLOCK

GENERATION GATE

0

SO 061

,0(50066 50191 50101

~

*

2321 ONLY

E

I/o

OPERATIONS DIAGRAM READ

DATE

I _I

I

^TY'E ^12841R

IB~ ¹⁴³¹

o

OPERATIONS DIAGRAM-Read

J/

(21)

( 2 I ³ I .. I ⁵ I ⁶ I 7

A

PHASE X BIT RING ADV

1 _

RS 021 _ _ BIT RING

a

(ST 4)

VFO OSC

PHASE BIT BIT FOR SET RO 041-- GATE FOR TO DR REG

r - GENERA- PHASE Y RING DELTA RING ADV RING ^{i - - - -} & RESET

TlON DRIVE I _'

10-

i - - - - SET FOR

SDI31 _{i - - - -} FOR RESET

50181 50121 50132

...

SO III

l ^B

FilE

L...-

DATA

A BU"RY VFO CTL REGISTER

CTR DRIVE COUNTER DECODE 8

-

r-RD~I-

& _~

--

BIT RING 4 DECODE ^~

DECODE 14

I - - -

DR REG BITS 0-7 SDI91

I

^SD201 ^SP091

-- _~gltJ

I -

SO 061

*

so 066

C

SEPARATED DATA

-

READ ClK GATE

L

^{t - - -}

~

ZEROS _{' - - -} DATA DATA READ

READ GATE HA 071 COUNT SEPARA- DATA GAP GOOD DATA GOOD CLOCK

CONTROL ^{I -} TION CLOCK GAP GATE

ADDRESS MARK HA 001 ZEROS COUNT SO 061

- ^... ^-

,'r 50066 50191

...

⁵⁰¹⁰¹

ONES RESET 50191

I

AM GOOD

0 I

ZEROS ^I-.

L

RESET

AM t - RESTART

SELECTED RAW DATA 50081 DETECTOR ^L...-.- ~TECTION AM NOT FOUND LATCH

10-

*50036

SO 031 50211 50101

*

2321 ONLY

E

1/0 OPERATIONS DIAGRAM READ ADDRESS MARK

DATE

I _I

I

^TYPE

I

2841&

I/O OPERATIONS DIAGRAM - Read Address Mark

IB~ ¹⁴³³