NEWMAN BERANEK

B 0 L T

BERANEK AND NEWMAN

^INC

C O N S U L T I N G D E V E L O P M E N T R E S E A R C H

i~---

CAMBRIDGE

Manual for the

IMP-1~

Special Interface to the Interface Message Processor

and the! ARPA Computer Network

October 1973

Computer Systems Division Bolt Beranek and Newman Inc.

50 Moulton Street

Cambridge, Massachusetts 02138

NEW YORK CHICAGO LOS ANGELES SAN FRANCISCO

Bolt Beranek and Newman Inc.

Manual for the

IMP-l~

Special Interface to the Interface Message Processor

and the ARPA Computer Network

October 1973

Computer Systems Division Bolt Beranek and Newman Inc.

50 Moulton Street

Cambridge, Massachusetts 02138

I

[ [

I

[

I

[ [

( [ [ [ [ [ [ [ [

I

[

Bolt- Beranek and Newman Inc.

TABLE OF CONTENTS

· 1 1.

2.

3.

INTRODUCTION.

INSTALLATION . . • . . INTERFACE OPERATION .

. . • 3

4.

3.1 Error Detection Logic. • . • • . 3.2 Operation of the Host-to-IMP Section . . 3.3 Operation of the IMP-to-Host Section . . LOG I C D RAW IN G S. . . . -. . . • • • . • . • •

. . ..

5. DESCRIPTION OF THE PROGRAM AND PROGRAM LISTINGS

6. WIRE LISTS . . • . . . • ^{II) 0 • • 0} • • • • • • •

APPENDIX A Selections from Report 1822 . . . •

• • 5 8 8

• 12 14

· • 26

· . 31

\ '

• • Al APPENDIX B

APPENDIX C

Devi ce Codes. . . . . • . . . _{· B1}

Card Layout, Special Cards, Delay Settings Cl

I I [ I [ [ [ I

I

[ [ [ [ [ [ [ I [

Bolt-Beranek and Newman Inc.

1. INTRODUCTION

The ARPA Network is being constructed to provide a capability for geographically-separated Host computers to communicate with each other. However, Host computers generally differ from one another in manufacturer, type, size, speed, word length, operating systems, etc. To allow these different computers to communicate, each Host is connected into the network through an Interface

Message Processor (IMP) located on the Host premises. The

complete network is formed by interconnecting these IMPs through wideband communication lines (initially 50 kilobits/sec) supplied by the telephone company. Each IMP is then programmed to store and forward messages to the neighboring IMPs in the network.

During a typical operation, a Host passes a message to its IMP.

This message is then passed from IMP to IMP through the network until it finally arrives at the destination IMP, which passes the message to the destination Host.*

The interconnection of a Host and an IMP is a joint effort that requires the Host personnel to provide,interfacing hardware and software. Bolt Beranek and Newman Inc. (BBN) has built a special interface to connect the IMP to a Digital Equipment Corp.

PDP-10 Host computer. This report describes the design, in- stallation, and operation of such a special interface.

Appendix A to this report reproduces Section 4 of the BBN Report No. 1822, "Specifications for the Interconnection of a Host and an IMP", which discusses the hardware requirements for

the special Host/IMP interface unit and describes the standard

*The initial IMP design is described in Bolt Beranek and Newman Inc. Report No. 1763 (January 1969), AD-682-905. The specifica- tions for IMP-Host interconnection are described in BBN Report No. 1822 (February 1970).

1

I

1\

~

[

I

[

I

[

[

I I I

[

I

[ (:

I

[

I

[

Bolt· Beranek and Newman Inc.

Host/IMP interface unit in the IMP.

Appendix B contains the device code and jumpering for specific installations.

Appendix C contains miscellaneous specific details of the hardware, including drawings of the display panel circuitry.

2

I I

[ [ [ [ [ [ [

I

[ [ [

I

[

Bolt Beranek and Newman Inc.

2. INSTALLATION

The interface will normally connect to an IMP that is no more than 30 feet from the interface. A special Distant Host option is required if the IMP is between 30 and 2000 feet from the interface. This option includes special cable drivers and receivers required to deal with the Distant Host version of the standard interface on the IMP itself.

The

IMP-l~

interface deals with the PDP-lO I/O BUS ex-

clusively. The interface is built out of DEC R, B, and W-series modules, mounted in two Type 1943 mounting panels. A Type 728 power supply is supplied, together with a Type 844 power control for protecting the I/O BUS circuits during power turn-on and turn-off. The circuit breaker and power switch on the back of the 844 control power to the interface.

The interface mounts in a PDP-10 rack, occupying 10-1/2 inches of front panel space for two baskets of logic cards, and 16 inches of back panel space for the 728 power supply and 844 power controller. The 5 1/411 display panel mounts at the front of the rack in the usual manner. Standard single-phase 115-volt power" with a third-wire ground should be provided by the Host.

The Host should also provide switched l15-volt power to drive the remote control relays in the 844.

The I/O BUS plugs into slots 25 through 28, and slots 29 through 32 of racks C and D, the lower basket. A type H004 block is supplied for mounting the I/O BUS connectors.

The IMP cable plugs into slot Dl, or, in the case of a distant Host, Dl and D2.

The device selection code is determined by jumpers on the W990 modules in slots D6 and D7. The jumpers should be placed as follows:

3

I I I I

[

I

[ [ [

I

[ [ [ [ [ [

I I I

For

Bolt Beranek and Newman Inc.

In order to effect the

device code in bit no. 3

4

₅

6 7 ⁸ 9

then pin E J M E J M R

on the

W990

ⁱⁿ

D6 D6 D6 D7 D7 D7 D7

should be connected

(to get a 0) to pin F K N F K N S or (to get a 1) to pin

D

H L D H L P the specific jumpering used, see Appendix

B.

4

I I I I I I

[

I I I I

[

I I

[

I

[

I I

Bolt Beranek and Newman Inc.

3 • I N T E R FA CEO P

E RA T

ION

To the program, the entire full duplex interface appears as a single device that has one DATAO (Data Out), one DATAl

(Data In), and one CONO (Conditions Out), and one CONI (Conditions In) instruction. Three interrupts are employed - - to indicate completion of an output word, completion of an input word, and completion of a message received from the IMP. These interrupts may be individually program-assigned to any of the seven inter- rupt channels. Thus, BLKO and BLKI instructions may reside in dedicated interrupt locations, or one interrupt routine may service two or all three interrupts, doing DATAO and DATAl

instructions functions. (Figure 1 shows the I/O Bus connections.) Communication from the PDP-IO to the IMP is started by a

DATAO from the PDP-IO. The interface will cause an interrupt on the "out" line to the PDP-IO on the 35th bit of each word.

The PDP-IO may then respond either with an additional DATAO, which transmits thenext word, or with a CONO, with the "END OUT"

bit set (see Figure 2). In the latter case, the interface will transmit the last bit to the IMP, with the "last bit" indicator set, and then interrupt the PDP-IO again. The PDP-IO may now respond either with another DATAO, to st~rt transmitting a new buffer to the IMP, or with a CONO with the "STOP OUT" bit set, which merely clears the interrupt. Input from the IMP to the

PDP-IO will cause an interrupt on the IN line each time a com- 'plete word is available. Upon receipt of the "last bit" in-

dicator from the IMP, the interface will pad with zeroes to the end of a PDP-IO word and then cause an interrupt, both on the IN line~ to indicate a full word, and on the END IN line, to indicate end of message. Note that the IN interrupt should be honored first, to complete the message, before servicing

5

.... . fIIIII!I'" ""1IIIIIIII

!I'III!I."

^{.. '"~.} ~--^{.. ~.'.}

fIIIIl .

..~",.,,,,,,,,.,

t""! !IfIIiII"liiiii

. . . . , .. ~ .~."' ... - ... " .. - ..

L ;

·.~w_"

!I'III!I

..• -.,-".",,~.~--,

!I'III!I fIIIIl

. ....-..

... ,.... ... ... ...

"-"~" ... ^~-.. ^~ .•. ^>~.. ..".,~-•.. "'''''' ... - .... ^~ - - .

_ :

'~"l'"

I

NOTE:

0\

o

I

S ^DEVSEL

DEVICE ADDRESS DETECTOR

I

I I I I I

I ^{I I}

r-I--L....-.L.--L-.I-...L..--LI---.. I

r ^I

I

^DECODER

I I

^DECODER

I I

^DECODER

I

I

^P25

I I

^P26

I I

^P27

I I

^P29

I r

^P30

1

^P31

1 I

^{P33 J P34}

I I

^P35

I

PRIORITY INTERRUPT LINES

GATES ALL' COND, CONI,

I I

THIS DEVSEL LEVEL

I

DATAO, AND DATAl SIGNALS.

I ~ ~ll ~Ll r~1 ~l ~h t-~~~ ~D ^. · · · ·

^~~

^cotJ ... ^co

^{w.\l _}

^{m ~m·}

^{I- co~ .. ~ ~}

.'

^{I <5!l • (ij}

^{!~Im-~ 15}

^{~ Q}

^{cop r .}

^{:2" Q ~1J}

^.1..1

^•

~.

^{-~ QJ}

^{~~ 1}

tlI,o' or

~' ~

^{Q" Q}

~

^{_ ) ' " y-}

I

^Q

i5

^{Q - - J \ " y PI IN}

\ 0 Y PI OUT

I

PI END IN - - - 1

- - I

- . -

1 ~I ~ ^C\I ~

ro

~I ~ ~ ~

a

^{~I ~}

108008 IOB018

I

^IOB35B

I __ _

~C~JERS

^[

]I{!IUITf!!lIIIill~~!!r!IrIIT-

1/0 BUS

t-~

¹

CONNECTORS 1/0 BUS DRIVERS _ _ - _ - B1 G]!:::=P35

DEVSEL ~'--•

\.. )

LEFT 18 BITS Y

- - - - I ~.

^CONI

.r;-l+==

IHB 35¹

L . . . : . . . k - L . _ _ .M-~-._-DATAl

\.. )

RIGHT Y'8 BITS

FIGURE 1 - I/O BUS CONNECTIONS

i ;

I . •

r

i

".

~.so

CONO FORMAT· .

RESET

CLEAR PDP-10 STOP

PEVICE

IIi MP HAS DOWN OUT

I

BEEN

DOWN"

^{I \}

, I

18 19 20 21

A

POWER PDP-10 IMP

UP DOWN HAS

BEEN DOWN

----

=

^~

_{~ ~ ~} ... ^{~ ~.-}

, ..

END GOT

EN

^{I I}

EN

OUT EN D PI END IN

IN B B

I I

I I

22

2y24

^{25 26/27 28}

I

IMP END END I I

DOWN IN IN PI END IN EMPTY

___ J~ __ L ___ .

^,

- - - - - - - - - -

FIGURE 2 CONO AND CONI FORMATS

..

I I

P I OUT

I I

I

2,;/30 31

I I

eI OUT

~

__

^l~

...

EN B P I IN ^I

_, ^I

I I ___

I

3~33 34 35 bit

I I

FULL P I IN

I I

, t-

CD 0

....

M"

g:,

CD -s

AI ::s

CD A AI ::s c..

z

CD ~

3

::s AI

-

::s n

II

~

"

II

II

₁

I I I

"I

:1

1\ ~

,I

~I

l

.1

;(

j 't~

( [ [ [

I I I

Bolt Beranek and Newman Inc.

the completed buffer. However, the state of the END IN line should be tested before executing the DATAl or BLOCKI, i f the two are

being serviced at the same priority level, since a new word (the last) may have come in between the execution of the DATAl and the next instruction. If that instruction concludes that the word i t just took was the last, a word will be lost.

3.1 Error Detection Logic

IMP failures are indicated by an opening of the IMP relay that connects the IMP Ready Test (ground) to the IMP Master

Ready line in the Host/IMP cable (see Figure 3). The IMP Master Ready line provides a bit in the CONI word and any opening of the IMP's relay is captured in the IMP-Has-Been-Down flip-flop, which provides another bit in the CONI word. This bit is cleared by one bit of the CONO instruct~on. Thus, the PDP-IO program can at any time test the state of the IMP. In addition, an IN END interrupt will be generated whenever the IMP becomes not ready.

The PDP-IO has a corresponding relay which is controlled by a bit in the CONO word. If the CONO IMP is issued with this bit clear, the relay is closed. If this bit is set on the CONO, the relay will open, and the Host will appea~ unready. The relay is also opened by CROBAR from the

844,

or by lOB Reset.

3.2 Operation of the Host-to-IMP Section

Figure

4

is a block diagram of the logic of the Host-to-IMP section. lOB reset presets the FIRST flip-flop to one. Upon receipt of the first DATAO from the PDP-IO, the 36-bit shift register is loaded from the 36 data lines. The MARK bit, to the right of the shift register, is set to one. One microsecond later, the shift register is shifted left by one position and the left-most bit appears in the HSDTA flip-flop and on the Host

8

I I

^t' _~

~ ;;

I11III

t_~1 ~

,.

\0

lOB RESET

It.O B'20 8

~ ~

fIIIIIII

CROBAR OPEN

eONO SET

~ ^{~ ~ ~ ~ @IIIIII ~ ~ I[IIIIIIJ}

- - - 0

HOST MASTER READY

P DP-IO

RELAY CLOSE

IMP MASTER READY I MP READY TEST

~.

-~ HOST- READY TEST

'"IMP

HAS BEEN DOWN

DOWN rMP

CROBAR C-ONO CLR

.GOTEND

FIGURE 3 - ERROR DETECTION LOGIC

fIIIIII!I ^{~ @IIIIJ}

to o

J-I c1"

to

(1) I-j I» ~ (1)

~

I» ~

0- Z (1)

I»

~

~ H

~ ()

-I _,

,

I

₁

i

I

I i

I

!

11 -~

ti ~

!~ !

~I ::1

~

~

~ ~

~f

....

-

o

....

i

...

^~

HSDTA

DATAO CLR

,....

^@IIIIIII ~

LHBIT

OUT CLR

--

^~

^fIIIIIIt

. STOP OUT CONO cLli

,l.OAD

"-

,

^{.. ' .}

:. CtE:AR

~ ~

~ IDATAO SET

o

...J

END OUT CONO CLR

FIGURE 4 - HOST-TO-IMP LOGIC

~ (IIIIIIt ~

....

HIMT

...

^II;

-

CLEAR

(DATAO CLR)

TYHB

END OUT

~CONO

SET

I I I I

[

I I I I I I I

[

I I I I

Bolt.Beranek and Newman Inc.

Data Line. The FIRST flip-flop is cleared at this point and the Bit Available (BTAVL) flip-flop is set. At that time, if the IMP is holding the Ready-For-Next-Bit (RFNHB) line true

(or shortly after the IMP brings this line true), the There's- Your-Host-Bit (TYHB) line is brought true. When the IMP indicates that i t has taken the bit, by bringing the Ready-For-Next-Host-Bit line false, the pulse generator is fired, shifting the buffer one bit to the left. A short time later, the interface again becomes ready to give a bit to the IMP. On each shift, zeroes move into the right end of the register.

This process continues for 35 bits. When the IMP confirms taking the 35th bit, the interface shifts the 36th bit into HSDTA and turns on the PlaUT flip-flop whichpresents an OUT

interrupt request to the PDP-IO. It also clears the Bit Available . flip-flop, so that the IMP will not be given the There's-Your-

Host-Bit signal (for the 36th bit) until the program has given the interface more information.

To send more words to the interface, the PDP-IO does further DATAO's (or a BLKO, wh1c~ looks like a DATAO to the interface).

Note that the "preshift", one microsecond after the DATAO, does not occur on words other than the first, since the FIRST flip- flop 1s not set. The DATAO causes the data word to be loaded into the shift register, puts a one into the MARK bit and turns on BTAVL. This gives the IMP the last bit of the previous word

(which has been held in the HSDTA flip-flop of the shift register), followed by the first 35 bits of the present word.

This process will continue until, after one of the interrupts, the PDP-lO informs the interface via CONO END OUT that the previous word was the last word of the message. At this point, the inter-

face will raise the Last-Host-Bit line and pass the last bit of

11

I I I I I I I I I

I I

[

I I I I I

Bolt· Beranek and Newman Inc.

the previous word to the IMP. The CONO END OUT also turns the FIRST flip-flop back on, so that the first DATAO of the next message will cause the "preshift" to occur.

When the IMP confirms receipt of the last bit, by bringing down the Ready-For-Next-Host-Bit line, the interface again inter- rupts the PDP-10. The PDP-10 may clear this interrupt either by

a

CONO STOP OUT, or by the first DATA

a

of a new buffer.

3,.

3

0

per'

at ion

⁰ f

the IMP - to .. H

⁰

s t Sec t ion

Figure 5 is a block diagram of the logic of the IMP-to-Host section. lOB reset sets the I'm-Ready-For-Next-Bit (IRFNB) flip-

flop. Upon receipt of a bit from the IMP, as indicated by the There's-Your-IMP-Bit (TYIMB) line coming true, the INPUT shift register is shifted 'one position to the left. Successive TYIMB's have the same effect until MARK bit is shifted into the leftmost position, indicating that the buffer is full. This causes an interrupt request on the IN line, and also clears the IRFNB flip- flop, to prevent bringing up the Ready-For-Next IMP-Bit line until the word has been taken by the PDP-10.

The trailing edge of the DATAl instruction clears the

buffer, sets the MARK bit, and raises the Ready-For-Next-IMP-Bit (RFNIB) line.

Upon receipt of the Last IMP bit indication, the interface clears the IRFNB flip-flop, to prevent bringing the Ready-For-Next IMP-Bit line true, and checks whether the input buffer is full.

If it is full, an interrupt request is raised on the END IN line.

If not, additional shift pulses are generated until the buffer is full. Note that the IMP Data line is gated off during this period by the falsity of the IRFNB flip-flop, thus forcing zeroes to be shifted into the buffer.

12

~:~.

. . . . ~ . . . ~ ~ .~ ~'~ ~ ~ . . . , . . . . ~ , . . . ___ . . . . 1 . . .

-

w

I

FULL

DATAl

TO PDP-10 I/O BUS

~---~~ ^\

r

~o ______ ~

35-BIT SHIFT REGISTER ru ^{I ~~!K}

+ ~ ^CLEAR

IMP DATA IRFNB

TYIMB I TYIMPJt SHIFT

DATAl

END IN

o

,Ir---"·INTERRUPT

, .

RFNIB"~---I

FULL

1" .

FULL

^~

,,~, .

lOB

t~

CONO CLR

.GOTEND ENDIN-

^I.

CL EAR

^<

" llBIT

FIGURE 5 - IMP-TO-HOST LOGIC

CONO CLR .GOTEND

~

TYIMP'

, \.

.~ ; ,

~,:>

I f

I;

[

I I I I

•• ~.. ~!ool·. .. ""'

Bolt Beranek and Newman Inc.

4. LOGIC DRAWINGS

This section contains the following illustrations:

Figure 6 IMP Error Detection Logic Figure 7 Pl OUT Channel Assignment Figure 8 Pl IN Channel Assignment Figure 9 Pl END IN Channel Assignment

Figure 10 I/O BUS Data Line Drivers-Receivers Figure 11 I/O BUS Control, Host Ready Logic Figure 12 Device Selection, Initialization Figure 13 -- Host-to-IMP (Output) Buffer

Figure 14 -- Host-to-IMP (Output) Control Logic Figure 15 IMP-to-Host (Input) Buffer

Figure 16 -- IMP-to-Host (Input) Control Logic

Figure 17a-- Local Host, Line Drivers and Receivers

14

....

1!IIIIIII1IIIIIIII~~!11!111111~~~~p!IIII!~fII!IIIIII~~I1111111111

...

~-

08198 H

R107 802 .

FIGURE 6 IMP ERROR DETECTION LOGIC

CXJ o

- A

ri' CXJ en

~

PI :::s en

7':'

:::s PI 0..

:z en :IE 3

:::s PI

-

:::s n

i

I

_:i

1 I

,~

j

I

.,

...

IIIIIIIIIIIII!IIIIIIJ~~

....

!IIII!II!IIII!II ... ~~!IIIIIIIIIIIIIIIIIJIIIIIIII

... I11111111_

....

0'\

;

PIE29- PIE29

E _~17

R203

129RSI~ ^D

oMYCOC E08288C

08298

~129RD F

RDlKMYCOC 816 L 08288-

M

08298- RI07 ':' 813

R111 816

PIOUT-

o

RMYCOC 5°8288-

~130RO T - ROOI

815

=1

^{C\I It) 'it It) CD ,...}

a.. a.. a.. a.. a.. a.. a..

0 0 0 0 0 0 0

-

^-

KI LI EI FI JI H

PIE30

08308- R111 814

N

08308

L

pr~ /R107

':' 813

K MYCOC 814 L 08288-

ROOl 815

PIE31- PIE31

5 TI817

ROOI 815 08318- R

08318 L Sr./RI07

-:- 813

FIGURE 7 - PI OUT CHANNEL ASSIGNMENT

R111 814

~ '<"'_""'A~"'~':' -->_~

.... I11III 1IIIIIIII JIIIIII !IIIIIIII ~ ~ !IIIIII L_i

t

_4 IIIIIIIIIIl L_ § t_A LuJi '_4 ~ I!IIIIII ... ...

...

"-..I

,

/ PIE33-

E

133RS

~

^D

o

^MYCOC RII1K~

E 08328- L 08328-

F

~133RO

o

^ROmE

C21

OB3158

I

E

f!J

Rl07 ^09339-

-=-

⁰²³

PIE33

R1I1 C22

08348

FULLO

ROOI C21

_ (\J ,..,

V 1.0 to I'-

n: -

-

0. 0. 0. 0. 0. 0.

o 0 0 0 0 0 0

~S

P U N T R

v

_1C24

8152 KI LI EI FI JI H

H F

08348- RI07

-=-

023

K MYCOC

L 08328-

08358

FIGURE 8 - PI IN CHANNEL ASSIGNMENT

PIE35 PIE35-

s

^Il£23

08358- J

Kr.IR107

-=-

⁰²³

R1I1 024

I

-

~ (X)

;

.... ^{IIIIIIIIJ IIIIIIIIl}

^{~ ~}

^fIIIIIIl

PIE25- PIE25

E .EL;>21 R111 R203 1J020

125RSI~ ⁰

o

^MYCOC

E 0824B~

08258

F ,...---C:>I-,.i 125 RO

ROOl 019

RDlKMYCOC .0

L 08248·

F

08258- Rl07

~813

R11I 020

~

L_'

~ ~ ~ ~ fIIIIIIIII

C\I~VlOtD"'"

-

-

^-

- - -

0.. 0.. 0.. 0.. 0.. 0.. 0..

o 0 0 0 0 0 0 ENOIN-

s

^P U N T R

v

_,022

orl 8152 KI LI EI FI JI H

PIE26· PlE26

RMYCOC S08248-

08268

J K IT • E>i126RO ROOI 019

L

08268-

"7813

K~

L 08248-

08278

FIGURE 9 - PI END IN CHANNEL ASSIGNMENT

[1IIIIIIII I

it ,

^__

^-'

PIE27- PIE27

s

!l.Q21

08278- RI07

"7 81 3

....

R11I 812

...

.... -

....

1.0 I'

IIIIIJ l1li L§

~

L~i~j.6L'i~ 71i'Tjw, L~g" t"gi;~ i i-' £'1r'" if l-"-iLrr;-"~'-l~M-""J1f,~,·tII1·I~-

08008 08018 08028 08038 08048 08058 08068 08078 08088

C25 \. T ^U T .. T n T " T ^IV' T r T ., T T 0

C29 \. A ^U A .. A n X " X ^IVI X r ]s ':. A A Y,)

010 08098

010 08108

010

08118 08128

010 08138

011 08148

011 08168

011 08178

::: ( I ~ I ; I : I : I :' I ~ I ; I ~ . I ~ )

011

08188 08198 08208

012 08218

012

08228 08238

012 08248

012

08258 08268

MYCNI " " " " n " n "

. 013 013 013 D14 014 014 015 015 015

08278 08288 08298 08308 08318 08328 08338 08348 08358

016 016 016 017 017 017 018

FIGURE 10

^~

I/O BUS DATA LINE DRIVERS-RECEIVERS

^{a.. .. ~ ~} s. "'"... ^{~ /''rJ} /)) ,A:';fX'f!

f /.

^{> 0}

,u . A'J _.

"'&' .

_r: ^j _'" ^{,., tf}

: \ .

i

~-:

...

N o

i

-

r--. !8

IIIIIIII

C32 r-..

0 E H K M P S T V

gg liliiii

.. 'A .. :· .. ~'.:liX~ ==w=rrei'4t2&¥ tHe NI jilt!] ~",~.:b iitit{~tift~1 0t'M$F.t ¥"#4-~ ._~«<Ii:'k , ... , i' ... i+rk"',~ .... .,..."',_~:..;;:_~~-, ,~. un ^"ootr

_.- I

r-,

----l!IIII!IlII!IIIIfIIIII!IIIIIIII~~~

...

^~

...

IE F ⁰

t

832 821 PWCLR

M R [

,

HMRoy HRoYT 5 800

J

~

I ~i

1000C _~ o ~ ^R113 F MYoOC- K ^RI07

^f-L+

^{MYoOC o}

^r

^R204AIO

¹

_~

_-b ~

RHRoy N ^~

832 821

J

^{L r R113}

1000S H K MYOOS- M ~MYoOS K ~ _ 831

R113 RI07 M ~

~ ^{08208- H} _J ^'1

1 ~R113

-:::- 831

832 830

~MYCOC

^~I

10COC L N MYCOC- 0

~ ^{R113 8165,}

P 832 830

~

^OB20B-

S MYCOS- H

~MYCOS OB208 E ^RI07

R113 BI65 A9

lOCOS ~

832 830

P 830 MyolB

10801 T MYoTI- L ~MyoIA

108CI U R113 8165

r

^{8165 toR}

830 ~

83l 0

0 F MYCNI- T

Iv1t

^{MYCNI E A Rl}

J.

^A!

R113 8165

E ^~

'WRUP 07

OEVSL

FIGURE 11 - I/O BUS CONTROL, HOST

RE~DY

LOGIC

.... • . . fIIIIII

fIIIII

~ ~ ~ ~

IIIIIIII

~

III!IIIII

~ ~

fIIIIIIII ... 1IIIIIIII

fIIIIII

IIIIIIII· . . .

BB

.E

10BRS- 10BRS H!>I RI07

' I. I

. I. I ~0S31

I· 1 "10S30

, I . I .10S41

B21

• 1 1 • 1 .10S40

• 1 1.1 .10S51

027 031

r " l ,-...

0 E H K M P

S

-

_V ^T

"---"

- -

..-

-

.-

-

.-

.-

-

..-.

- ...

10S50 10S61 10S60

10S71 10S70

10S91 10S90

F

A6

o

F K

V

W800 005

L ~ N MYCNI R002 P ... S MYOIA

003 T ~ V

- - - S - :.tvt.Y0l6. - -

R001 R PIE25

~!~

_.r __ .:g __

eI.E2Q. __

o

^{E PIE27}

PWCLR ^{F H} PIE29 K PIE30 A07

R001 L M

PIE31

N P

PIE33 CROBAR

from 844 R S PIE34 T ~PIE35

OEVSL- M

E OVSB3 0 R107

-:;: 023 J OVSB4 E

Rl11 -:::- Bll

--~"""11 ... ! ^1M

^OVSB5 _R001

^~~VXPN

C20

0 F H

• •

• •

·1006

•

E OVSB6 F J OVSB7 J

H

R001 IC20 K

---,

M

~C20

p

FIGURE 12 - DEVICE

SELECTION, INITIALIZATION

'.

i l

r _'1

1 1

"

t ' il·

\1

II til

'~IJ

~

I

~ ,

!I

I I

I

I

t:

^{% ...}

!i ! N

!i:~~

~~I'r---'

>~

^{CI) Bv£BO I %B!l£BO}

~~I' ~I-~-

+!l£BIH ~II 1 C l : l ^> +9£BIH~11 ~ +.I.£BIH~ 1 C l . . J " ' 1 C l t' ^{> ! %} ii:~ ^I'

z ... 0 l(l!..~ ⁰ "'~, ^{0 I-} a:

; ~ ~ &! ^I- CD ~I=Z &! "~h·1L1: ~ H., jl' ^I CI)

-!l£BIH a:~ ^{z -9£BIH ...} ~ ⁰ -~IH'I::: ^{z :l}

Jlij!.

~I-

~

CI) % XCI)

0::

LLJ LL.

LL.

0- ;::)

::::E: CO

I

-

^I

_-

M 0 I-

-

_LLJ ^{I -}_{l -}^I _I-^{;::) 0-}

0:: ^{V) ;::)}

;::) 0 0

t!l ::r:: ...

-

LL.

I B.LZBO_ I B8ClBO I B6ClBO I B0£BO I BI£BO I BCl£BO I B££BO

+8Cl91H r--f.jII..ol-f::E".+:!6Z",s",-IH"t----::-l > +0£SIHr-- II ::E +I£BIH - I I > +Z£IIIHr---11 ::E +££8IH~ II > +v£BIH -~H::E7-'-+ ... !l£",8,,-,I,,-,H CI) -. ICl ..J N

>...

^IClO ^:;)N> ::! U')o ..J_ ... !- ^ICl_O ^::> 1Q1L. .., It) ..J Q. I(') ::> ..., lO ..J

IM.:a...{;; 2 _: ji!~i'" r,-IG,i'" .. ~~ 0 l(l~~ 0 "'~F 0

iii "<i:I'" 0:: "Rlfo:l~ &! I-CDl~l~ &! "RI Cl~ ~ I- I"'l~ &! "CDLM~ &! I-Rl"-;l::Z &!

-8ClBlH "'~ c~_-6_Z_B_I_H4-^{__ 0: __} ~ ^__ "'4-~Z~~~-0~£B~~~~ ^__ "'~~C~+--+~_I£B~f_H_-^__ "'+-z~~41~-Z~£8~"'_~_~ ^__ "'~_C~r-~-_££B ^__ ~_~ ^__ "'-+~z~+--i-_v£ ^__ :_rn_~

__

"'4-~c~r-,-!l£BIH

e

::Er---~--+_--~----_i--~_i---r__i--r_----+_--ri+_----_r--+__r----_+--_r_;

%

CI) % CI) ::c CI) ^:J:

I

B0ClBO I

BIZ80

,1

BCl<l80

11

B£ClBO II 8l>ZBO I BSCl80 II

+I<lBIH

-

>+ClCl8IH

-

::E +£ZSIH r-;;;- ^{> +IoZBIH- ::E +SZ8IHr-- > +9Z8IH~} ::E +l28lllr--

N~~ ^{ICl :;) o -, ICl -IN ~ 0. 0 :J ~ "':II It) ..J} ... ^ICl J(\JZ;; 8 _~~ U) CL

0 ICl

N~~ ⁰ N~~ ^{N N It) 0} ;~ ⁰ _I-Rl~~ &! ⁰

S! ⁰ ~ ^C\I 0:: I- ~ w ^{<[ C\I} 0:: ^:!I£ID :r: oCt a: .... ~~~ ~ ^C\I ~CD~~ ^C\I

" ^...

'"

^{0:: 0::}

-IClSIH _0:-.;: -ClZSIH "'-,;: ^{-£ZSIH 0: '-I;: -PClBlH "'~} -SCl8I~'---;;: -9Cl8IH '" '--;;: -.I.Cl8IH 0: """I;:

z 0 z 0 z 0 z

::c ^CI) ::c ^{CI) :J: CI)}

- I I 8£180_ ,I 8l>180 II BSI80 II 891BO II 8.1.180 11 ⁸⁸¹⁸⁰

J

+vI9IH ::E+SI9IH > +91SIHr-- ::E +lI1I1Hr-- > +818IHr-- ::E +6ISIH~ > ~~IHr--

& LL ~ 8 ... "

...

^{ICl :;)} " -. ^{ICl ..J Z ... ICl :;)61 -, ICl} ... CI) ...

8

^{:;) -. ICl}

6I~t ⁰ I-~ ~~ ⁰ ,,~ _-f3l~ ⁰ ~~ ^{0 re ~: C\I} ~~ ⁰

RI~~ ^C\I 0:: " ^{N CD} :J: '" ^{N C\I} 0:: ^C\I 0:: ^C\I 0:: I-CD ^N ::E'" ^{C\I 0::} "CD ^Q. ~ ^0: I- 0:'" ^C\I 0::

-vI9IH

"'---.:: 0 ^{-SI8IH o:~} z -918::: ^{"'I;: 0} -.1.18:'-;;:: z -919::.' '-;;:: 0 -619~""'"""i;: z -0Cl:::H"""I;: ⁰

CI) :J: CI) :J: CI) ^:J:

- , I 990BO ,I 9.1.080 II 99080 II 860BO II 80180 II 81180 !I

+.I.081H > 9IIlIIIH- ::E f6081Hr-- > +018IHr-- ::E +118\11r-- > +ZI8IH- ::E +£ISIHr--

~~l ^ICl ₀ ^{:;) z -, ICl ... Vl ... II) :;) CI) -. ICl ... > ... ICl => > -. ICl ..J ...}

...

^ICl

"'~f ^{0 !!!~: 0} '" _~~ ⁰ '" ~~ ⁰ '" ~~ ⁰ fol~ ⁰

III ... '"

C\I I- 0; ::E <i ^C\I ~CD a.. <i ^{C\I 1-0; C\I} _"iii ^C\I ... iii ^{C\I C\I}

0:: 0:: 0:: 0:: 0:: 0:: " ^0::

-.I.08IH _0:-.;: -90BIH "'---::- -609IH 0: ' - -

-018:::'-1;: ~181:'-I;: -C::18I~~ -~18~ ^----.:

z -.:: ci ... z ⁰ z ⁰ z

10-

,~ ^{Vl :J: Vl ::c CI)}

I r RI 8IHl:l!1 80080 II 81080 II 9Z0BO II 8£080 11 8l>0BO

.1

+00BIH

-

^{::E +I08IHr--} > +Cl08IHr-- ::E+ £08IHr-- >+ l>08IHr-- ::E +S08IHr-- > 908IH-

-. ^{II) ..J}

...

^{ICl :;) -. ICl} ..J ... ... ICl _:;) ... ^{-, ICl ... ... ICl :;)}

~; ^ICl

II) 0

'" ^{0 .,. 0 !!!~.,. 0} "'~r ⁰ !!!it~ ~ ⁰

~ ^C\I 0:: <i ^C\I ... <i &! ^{C\I , . ..iii w 4: C\I C\I}

" ^{0:: ~m 0 ct 0:: 0:: ~CD % <l 0:}

...

_-.'" ^0::

-008IH "'-- ^{-1081H 0: _ _ _} -<:0BIH ... ~ -£0BIH 0: '-u:: -l>0BIH "''-u:: ^{-!l08IH o:~} - 9081H", -;:;:r

0 z ⁰ z ⁰ z ⁰

22

CI) B9ClBO

> +8ClBIH

:;)

I- -8Z9lH

:J:

96180 ::E +1<l8IH

...

" -1<:8IH

CI) BZIBO

> +l>18IH

:;)

...

-vlE!IH

t-

8!O080 :IE +.I.09lH ..J

-.I.e9tH

. . . ;,.;;' ...

~~l;J7~"@III~~'. ~;'"

__

i~Jl.' "lIft'~ .~

...

~,s~if/"'

..

It'P~~;·',"~~;.r~b.~.l

...

~.:-

.. ;."

^-<.,'

'~':#' }t;,4~;'"~"._";~

^...

:._,,,~L. ~.~.~~~~=_.·._~~2i.i:.fl:~ .. i.,("w-.:._~_, ,!~~

^.,.::':.'

e':'::!~f;;'~~~~''''::'-=~~'~~;' ~';*,~tstiH"Hw;W8'

N W

/

RFNNB 0

o

MYDOS- E

E -:-

6TAVL DISPU

~ R107 023

. .

F

RJ13 610

MYCOS~

06226-Df"

PRPLS- -S--

R113 601

PIOUT '~L

ENOOX

MYCOC 06216-

STOPOD

R113 601

PUlSH~M V~T

SAt. •

R6QJ3 ~R603

608 608

PWCLR

FIGURE 14 - HOST-TO-IMP (OUTPUT) CONTROL LOGIC