The Timed Message Passing model (TMP)

The Timed Message Passing model (TMP)

- Each network node has a local hardware clock H -

- There is a bound d on end-to-end message transmission and processing time

- We defined logical clocks and skew

- Uncertainties: hardware clock drift, and

message transmission time

2

Computer Time

H, L

UTC time, t

Perfect time

3

Computer Time, H

UTC time, t

Perfect time

Hardware clock envelope

skew

4

Computer Time, H

UTC time, t

Perfect time

Our Model

(drift faster than real time)

skew

5

Computer Time, H

External reference time, t (linear bound to UTC) Perfect time

Alternative view skew

Accumulated Skew ≤ �(� -1)

6

Computer Time, L

External reference time, t

Minimal

linear bound on Logical clock rate Logical clock

Synchronization algorithm Intend to maintain

a bounded Skew

It can slow down logical clocks

(even slower than minimal H)

MAX algorithm – APOLOGY

L ^a (t ⁴ ) – L ^b (t ⁴ ) ?

RECALL: the difference between the values of the hardware clocks of v and w may increase by �(� -1)

t ⁴ t ² t ³

t ¹

a b c

L ^c L ^b

L ^a

d d

�d L ^b (t ⁴ ) = L ^b (t ² ) + L= L ^a (t ¹ ) + L L ^a (t ⁴ ) = L ^a (t ¹ ) + L’+ � d

L ^a (t ⁴ ) - L ^b (t ⁴ ) ≤ T (� -1) + � d T

L

L ^a (t ⁴ ) - L ^b (t ⁴ ) ≤ L’- L+ � d L ^a L ^b

L’

MAX algorithm – maximum clock dif

L ^a (t ⁴ ) – L ^b (t ⁴ ) ? t ⁴ t ² t ³

t ¹ L ^a

a b c

L ^c L ^b

L ^a

d d

L ^b

�d L ^b (t ⁴ ) = L ^b (t ² ) + L= L ^a (t ¹ ) + L L ^a (t ⁴ ) = L ^a (t ¹ ) + L’ + � d

L ^a (t ⁴ ) - L ^b (t ⁴ ) ≤ T (� -1) + � d L’

L

L ^a (t ⁴ ) - L ^b (t ⁴ ) ≤ L’ - L+ � d

L ^a (t ⁴ ) - L ^x (t ⁴ ) ≤ T (� -1) + � dD

T

MAX algorithm – maximum clock dif

t ⁴ t ² t ³

t ¹ L ^a

a b c

L ^c L ^b

L ^a

d d

L ^b

�d L’

L

L ^a (t ⁴ ) - L ^x (t ⁴ ) ≤ (T+dD) (� -1) + dD T

L ^a (t ⁴ ) - L ^x (t ⁴ ) ≤ T (� -1) + � dD

MAX algorithm – First Synchronization

L ^a (t ⁴ ) – L ^b (t ⁴ ) ? t ⁴ t ⁰

t ³ t ⁰

L ^a L ^b

d

L ^a (t ⁰ ) - L ^b (t ⁰ ) = H

L ^a (t ⁴ ) - L ^b (t ⁴ ) ≤ (T+d) (� -1) + H

T L

L ^a (t ⁴ ) - L ^x (t ⁴ ) ≤ (T+dD) (� -1) + H

increase by �(� -1)

The Timed Message Passing model (TMP)

- Each network node has a local hardware clock H -

- There is a bound d on end-to-end message transmission and processing time

- We defined logical clocks and skew

- Uncertainties: hardware clock drift, and

message transmission time

The Timed Message Passing model (TMP)

- Each network node has a local hardware clock H -

- There is a bound d on end-to-end message transmission and processing time

- We defined logical clocks and skew

- Uncertainties: hardware clock drift, and message transmission time

- Is there an algorithm than can obtain a

constant skew or O(d) skew?

13

w v

t

t

t

If t ³ -t ¹ =2d we can synchronize the logical clocks L ^w =L ^v (t ² )+d.

If t ³ -t ¹ =d we face a problem

14

w v

t

t

t

If t ³ -t ¹ =d we face the basic uncertainty.

d

t

t

15

w v

t

t

If t ³ -t ¹ =dD we face the basic uncertainty.

dD

The basic uncertainty – given no drift hardware clocks

w

v ⁷

7

8

8

9

9

10

10

11

11

w

v ⁷

7

8

8

9

9

10

10

11

11

w

v ⁷

7

8

8

9

9

10

10

11

11

All events take place

at the same clock time

in all 3 scenarios

A State Machine in TSM

Inputs / messages

messages outputs

state

The sequence of messages and outputs depends solely on 1. the initial state and initial input

2. the sequence of messages and inputs it receives 3. hardware clock readings

H

18

Computer Time, L

External reference time, t

Lowest rate of progress

c �

Lower bound proof

Assume existence of a logical clock algorithm that satisfies the amortized minimum progress.

In the presentation we assume that the uncertainty is d

(in the text it is u ≤ d)

20

w v

t

t ¹ +x

Timely behavior: drift=0, message transmission=d/2 Scenario 0. H=0, and timely behavior

D

H ^v =x

Lower bound proof – 1st step

By playing with drifts and message delays we start from all H=0 and

introduce a sequence of intermediate scenarios that

step by step, after some time x, reach a point where one of the nodes have hardware clock value of

H ^v =x+D(d - ), �

without any node noticing the difference among any two consecutive steps.

All other clocks equal x.

View after time x.

w v w

v ^H

=x+D(d/2- ) �

w v

Scenario v

Scenario w Scenario 0

H

=x H

=x

H

=x H

=x

H

=x+D(d/2- ) �

Lower bound proof – 2nd step

We have no idea how the synchronization algorithm adjusts the logical clocks in these scenarios.

• We claim that in any synchronization algorithm, at some time after time x, the sum of

the increase in logical clock value of w in scenario v, and

the increase in logical clock value of v in scenario w need to satisfy

� L ^v + L � ^w ≥ D(d - ) � 3�

• We assume to the contrary and introduce sequence of

steps with a slower rate ’≤ that eventually reach a � �

contradiction

24

Computer Time, L

External reference time, t

c �

Assuming L � ^v + L � ^w < D(d - ) � 3�

We obtain a contradiction to the

minimal assumption �

View after time x.

w

v ^H

=x+D(d/2 - ) �

w v

Scenario v

Scenario w

H

=x

H

=x

H

=x+D(d/2 - ) �

v and w can’t tell the difference – so their logical clocks are the same in both scenarios.

therefore L � ^v � L ^w actually represent the skew

in the appropriate scenarios

Lower bound proof – final step

We observe that L � ^v � L ^w actually represent the skew in the appropriate scenarios, therefore at least one of

them satisfy

� L > D(d - )/2 � 3�

Since we can choose arbitrarily small, we end up �

proving

Updated MAX algorithm

Assume – the logical clock L ^v is updated in the background at the rate of the hardware clock.

The algorithm is invoked upon these events::

wakeup, receiving a message, or on timeout 1. Wakeup: L ^v :=H v (performed only on wakeup)

2. If received l’ and l’ + d - u> L ^v L ^v :=l’ + d - u – update logical clock

3. If H ^v =kT then send <L ^v > to neighbors

(performed at the same clock time as line 2)

Notice: updating the logical clock is done by adding the

difference (l’ + d – u – L ^{v) to} L v – or resetting L ^v