TTL I/O Card

STD 7000

7604

TTL I/O Card

USER'S MANUAL

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TTL 1/0 Card USER'S MANUAL

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7604 TTL I/O CARD USER'S MANUAL TABLE OF CONTENTS

SECll0N 1 Product Overview

SECTION 2

SECTION 3 SECTION 4

SECTION

5

SECTION 6 SECTION 7 SECTION

8

SECTION 9

1 IT I I A ' I

- Block Diagram Functional Description

- General Purpose Interface Mapping

Address Decoder Operation

- Changing the 7604¹s Port Address 7604 Card Environmental Specification Electrical Specifications

Mechanical

7604 Operating Subroutine Modules Maintenance

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~@@ _.- 7604

.r:',:,I~~~~~~~~TTL I/O CARD

TTL INPUT/OUTPUT CARD

This card provides 8 ports of which any number can be input or output ports or output ports with read back (64 I/O lines total). .

The ports are accessed at 16-pin DIP sockets on the card.

The output lines are TTL compatible with the ability to drive 16 low power Schottky TTL Loads each (4 TTL loads). A reset line is available· to clear all output ports simultaneously.

The input lines are TTL compatible with an input rating of 4 low-power Schottky loads.

The ports are configure'd as input or output ports simply by removing the unused Ie associated with that port. If the input buffer is retained. output port data may be read back into the Processor.

The 7604 decodes eight address lines with provi- sions for expansion and memory mapping, An on- card jumper system allows users to establish the eight consecutive port addresses occupied by the 7604,

FEATURES

• 8 Ports conflgurable as Input or output or output with readback

• User selectable port address (256 port field)

~ Outputs Drive 16 low-power Schottky TTL loads

~ Provision for expansion and memory mapping , All ICts socketed

• Single +5V operation

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FUNCTIONAL

The 7604 is shipped fully populated. The card is customized (to A input and B output ports such that A + B

=

8 ports) by removing the unused input buffer or output port latch according to the following table.

OUTPUT PORTS INPUT PORTS PORT NO. IC NUMBER IC NUMBER

Port 0 U17 U9

Port 1 U19 U11

Port 2 U21 U13

Port 3 U23 U15

Port 4 U16 U8

Port 5 U18 U10

Port 6 U20 U12

Port 7 U22 U14

Leaving the input butfer in at output ports allows the Processor to read back the output port data to check for noise alteration or to use the output port as a data register.

The 7604 provides 64 alternating data and ground lines. These signal lines can be up to 10 feet (3.0Sm) long with proper electrical considerations. When writing to an eight bit output port the data bus data is latched in the output port. The output data will remain latched in that state unti 1 it is written to with new data

or the SYSRESET* signal clears the port. When reading from an 8-bit input port the stat~

of the port lines at the time of the read is transferred to the data bus.

RESET

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The SYSRESET line clears all eight output ports to zero simultaneously. On,system

power-up the SYSRESET signal clears the output ports.

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GENERAL PURPOSE INTERFACE

The 7604 is usefu 1 as a gene ra 1 purpose TTL interface ca rd. Iff 1 at cab 1 e or tw i sted pair discrete wire cable assemblies are used, the ground-signal-ground of the I/O connectors mfnimizes crosstalk between inter-system signal lines in electrically noisy environments.

DATA BUI

BUFFER

FROM

PORT·SELECT OECOOERS

-5V

q:7K

Qr---t---<==~

OUTPUT STROBE

RESEr _ _ _ _ _

lH9UT ST-.o&. _ _ - , . J t # ....

FROU OTHER CIRCUITS

TYPICAL I/O CIRCUIT FIGURE 2

74LS244

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3.

Card Address Mapping

The 7604 Card is selected by a decoded combination of address lines A3-A7. The user chooses the card address combination by connecting one jumper wire each from SX and SY to pad matrices adjacent to U3 and U4 (see diagram).

The 7604 is shipped mapped at Hex Port Address 00.

To map the 7604 anywhere in the hexadecimal add ress range 00 to FF, change the decoder outputs connected to SX and SY.

Port Addresses

Address lines AO. A 1 and A2 select one of eight Port addresses. One input port and one output port reside at each address. The RO- and WR- inputs control the input gating and output latch functions.

~ ADDRESS DECODER OPERATION

Refer to the schematic, Document #104483.

The 7605 uses four cascaded 74LS4Z decoders (U3, U4, US and u6) to decode address lines AO-A7. These decoders are enabled only when 10RQ* and 10EXP* are active.

Address lines AO, AI, AZ and the WR~~ signal are used to gate the select strobes from u6 that control the output ports. Address lines AO, AI, A2 and the RD* signal are used to gate the select strobes from U5 that control the input ports.

CHANGING THE 7604's PORT ADDRESS

Refer to the Assembly diagram, Document #104484.

Locate decoders U3 and u4 (74LS4Z) adjacent to the STD BUS edge connector.. Each decoder device has a dual row of pads which form decoder output select matrices.

Make one (and only one) connection to each of the matrices adjacent to U3 and u4.

The decoder jumper pads numbered as shown in Figure 3 are adjacent to the decoder

chips on the 7604. Also shown are the jumpers (at XO and YO) which produce hexadecimal port addresses 00, 01, OZthru 07, the selections made when the card is shipped.

Card Address Selection

FIGURE

3

imAA

The I/O address mapping and jumper selection table for eight addresses per card shows where to place jumper straps to obtain any eight sequential port addresses

in the hexadecimal range OO-FF. Using the lower of the 2-digit hexadecimal addresses desired, find the most significant hexadecimal address digit along the vertical axis, and the least significant hex digit on the horizontal axis. For example, port addresses 00,

ot,

02 thru 07 are obtained by connecting jumpers at XO and YO.

The only restriction that applies in address selection for the 7604 is that the lower of the eight port addresses (00 as shipped) must occur only at every eighth possible address; for example, the sequence 01, 02, 03 thru 08 is not allowed by the decoder.

The pad matrices adjacent to U3 and U4 are on 0.10 inch (0.25cm) centers. The jumper wires may be conveniently replaced by wi rewrap post if frequent address selection changes are anticipated.

MOST LEAST SIGNIFlc.un' HEX ADDRESS

JUMptA SIGNIFICANT

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⁷ ' T t 1 A f , f C l o 1 E 1 F SELECTION HEX AODR£SS

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1 XO Y2 xo '1'3

2 Xl YO Xl '1'1

3 ^X1 '1'2 Xl '1'3

4 X2 YO X2 '1'1

5 X2 '1'2 x2 '1'3

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8 xs '1'2 )(5 Y3

C x6 yo _{XI; Y1}

0 x6 '1'2 )(6 Y3

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F XT Y'l )(7 Y3

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I/O Address Mapping And Jumper Selection Tables For 8 Addresses Per Card

FIGURE 4

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⁷⁶⁰⁴ CARD ENVIRONMENTAL SPECIFICATIONS

R£COMMENDED OPERATINb LIM I TS ABSOLUTE ~ON-OPERAT'N' LIMITS

PARAMETER MIN TY? MAX MIN

MAX

UNITS

Free Ai r TemperatIJre ₀

25 55

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75 °c

Humidity

CD

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Non-condens i n9

,. ELECTRICAL SPECIFICATIONS

7604 GENERAL PURPOSE TTL I/O CARD ELECTRICAL TEST SPECIFICATION

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RECOMMENDED OPERATING LIMITS ABSOLUTE NON-OPERATING LIMITS

MNEM. PARAMETER

MIN. TYP. MAX. MIN. MAX. UNIT

Vee Suppl,y voltage 4.75 5.00 5.25 0.0 7.00 Volt

TA Free air temp. 0 25 5S -40 75

°c

USER WORST CASE ELECTRICAL CHAR~CTERISTICS OVER RECOMMENDED TEST LIMITS For I nput Port

PARAMETER

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^{MIN TYP MAX UNIT}

VIH High level input vo 1 tage 2.0 V

VIL Low 1 eve 1 input voltage 0.7 V

Hysteresis (VT+ - VT-) 0.2 0.4 V

for Input current each port 1 ine represents 4 LSTIL loads

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PARAMETER

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MIN TYP MAX UNIT

VOH High l~vel output voltage

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VOL low level output voltaQe

A

^{0.35 0.5 V}

Each output can drive 16 lSTTl loads*

* 1 LSTTL load - O.4mA

STD BUS ELECTRICAL CHARACTERISTICS OVER RECOMMENDED TEST ll~ITS

PARAMETER ^MIN TYP MAX UNITS

ICC SUPPLY CURRENT 450 700 ^rnA

STO BUS INPUT LOAD See Figure

6

STD BUS OUTPUT DRIVE See Figure

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Input characteristics with output chip removed.

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Output characteristics wi th input chip installed.

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MECHANICAL

· Meets all STO BUS general mechanical specifications

· May require one additional card slot width for ribbon cable access to ports (connector dependent).

· Connectors use low profile l6-pin DIP plugs with heavy

duty pins. T and B Ansley Catalog No. 609-M165H or equivalent.

mmI mEl

U1 U16

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U2 U9 U17

74L5244 ₁₀ 74LS244 74LS273

Ul0 U1I

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U12 U20

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U13 U21

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7604 ASSEMBLY FIGURE 5

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Input/Output Port Socket

STDI7604 EDGE CONNECTOR PIN LIST PIN NUMBER PIN NUMBER

OUTPUT (DRIVE) OUTPUT (DRIVE)

INPUT (LOADING) INPUT (LOADING)

MNEMONIC MNEMONIC

+5 VOLTS VCC 2 1 VCC +5 VOLTS

GROUND GNO 4 3 GNO GROUND

-5V 6 5 -5V

07 1 60 8 7 60 1 03

06 1 60 10 9 60 1 02

05 1 60 12 11 60 1 01

04 1 60 14 13 60 1 DO

A15 16 15 1 A7

A14 18 17 1 A6

A13 20 19 1 A5

A12 22 21 1 A4

All 24 23 1 A3

Al0 26 25 2 A2

A9 28 27 2 A1

A8 30 29 2 AO

RO' 1 32 31 1 WR'

MEMRO' 34 33 1 lORa'

MEMEX' 36 35 1 IOEXP'

MCSYNC' 38 37 REFRESH"

STATUS 0' 40 39 STATUS l '

BUSRO' 42 41 BUSAK'

INTRa' 44 43 INTAK'

NMIRO' 46 45 WAITAO'

PBAESEr 48 47 1 SYSAESer

CNTAl' 50 49 CLOCK'

PCI IN 52 51 OUT PCO

AUX GNO 54 53 AUX GNQ

AUX-V 56 55 AUX ·V

"DeSIgnates ActIve low Level logIc

Edge Connector Pin List

FIGURE 6

• Address. Data and Control Busses meet all STD BUS general electrical specifications except AO.

A 1 and A2 which are 2 LSTTL loads each,

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8.

7604 OPERATING SUBROUTINE MODULES

This section provides flow diagrams and subroutines to operate your 7604 card. These may be used intact, or used as models to construct subroutines for a specific

ap~lication.

The subroutines are written in 8080-fami1y assembly code and wi 11 execute on 8080, 8085, and z80 processors. The memory addresses selected are compatible with Pro-Log's 7801 (808SA) and 7803 (Z80) processor cards. The 7604 port addresses used are

the address jumper selections made when the 7604 is shipped.

To use these subroutines in systems other than those described above, the ~emory

andlor lID port addresses may require change for compatibility.

The flow diagrams presented can be easily translated into the assembly code used by any microprocessor since they show the steps required to achieve 76d4 operation without reference to a particular microprocessor.

The (check bits) subroutine wi 11 compare the present input port status with the port status from the last time that the port was read.

To use the routine the HL pointer must point to a place in memory where port status is stored. Also, the port must be read into the accumulator before calling the routine.

Upon return from the routine the location that the HL pointer was previously set wi 11 contain new port status. Plus the next four locations will contain change status.

Uses Registers A, Hand L

1

M XX New Data +-Location HL was set to M+l XX Old Data

H+2 XX Changes M+3

xx

Bits to Zerc M+4

I

^XX Bits to One

Memory after Return

The (set bit) routine can set a bit or bits on an output port. To use the routine load the accumulator with the bits that should be changed.

(Input chip must be installed)

The (clear bit) routine can clear a bit or bits on an output port. To use the routine load the accumulator with the bits that should be changed.

(Input chip must be installed)

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INPUT PRESENT STATUS

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OUTPUT NEW STATUS

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INPUT PRESENT STATUS

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OUTPUT NEW STATUS

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