Input/Output 7601

STD 7000

7601

Input/Output Port Card

USER'S MANUAL

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7601 TTL OUTPUT PORT CARD USER'S MANUAL

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F CON TEN T S

SECTION 1 Product Overview Block Diagram SECTION 2 Functional Description

General Purpose Interface SECTION 3 Mapping

SECTION 4 Address Decoder Operation

Changing the 7601 Port Address SECTION 5

SECTION 6

7601 Card Environmental Specifications

SECTION

7

SECTION 8 SECTION 9

PRO-LOG

FORM NO. 101905

Electrical SpeCifications Mechanical

7601 Operating Subroutine Modules

t~a i n tenance

CORPORATION

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®If[Q) [ID(!JJ®~~~INPUT /OUTPUT PORT CARD

TTL INPUT/OUTPUT PORT CARD

This card provides four 8-bit gated input ports (32 input lines) and four 8-bit latched output port (32 output lines).

Input port lines and output port lines are accessed at 16-pin DIP sockets on the card. 1/0 lines are TTL compatible with an input rating of 4 low-power Schottky TTL loads and an output drive rating 01 20 low-power Schottky TTL loads (5 TTL loads). A reset line is available.

The 7601 decodes eight address lines with provision for expansion and memory mapping. An on-card jumper system allows users to establish the four consecutive 1/0 port pair addresses occupied by the 7601.

FEATURES

• User selected port address (256 port field)

• Input rating: 4 LSTTL loads

• Output rating: 20 LSTTL loads (5 TTL loads)

• Provision for expansion and memory mapJ)ing

• Input buffers have 200 MV of hysteresis for additional noise margin

• Input lin .. include 4.7K pullup r.sistors

• All IC's locketed

• Single +5V operation

...-..-.,-... -1 OAT A

10RO· ( ' ) - - - 0

AD· o - - - a ^PORT

WR· 0---0

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ADDRESS O--:"~-I .4o-A1

SYSRESlT· 0 - - - 0

IN~/OUT~UT PORTS SHADING INDICATES" SOCKETS

FIGURE 1

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1/0 PORT CONNECTORS

7601

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2. FUNCTIONAL DESCRIPTION

The 7601 provides 32 TTL output lines and 32 TTL input lines. All signal lines are alternated with ground lines. These signal lines can be up to 10 fe'et (3.05m) long with proper electrical considerations. All port lines are addressable in eight bit bytes.

OUTPUT

When writing to an eight bit output port the data bus data is latched in the output port. The output data will remain latched in that state until it is written to with new data or the S¥SRESET* signal clears the port!

RESET

The SYSRESET* line clears all four outout ports to zero simultaneously.

The input ports are unaffecteo. On system power~up the SYSRESET* si~nal

clears the output ports.

INPUT

When reading from an eigh~ bit Input port, the state of the input lines at the time of the read is transf~rre~ to the data bus.

GENERAL PURPOSE tNTERFACE

The 7601 is useful as a general purpose TTL interface card. ~f flat cable or twisted pair discrete wire cable assemblies are used, the ground~signal­

ground of the tlO connectors minimizes' crosstalk between inter--system signal lines in electrically noisy ~nvironments.

PRO-LOG CORPORATION A

FORM NO. 101905

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3. CARD ADDRESS MAPPING

The 7601 card is selected by a decoded combination of addres.s 1 tnes· A2 through A7. The user chooses the card address combination by connecting one jumper wi re each from SX and SY to pad matrices' adjacent to U3 and U4.

(See Assembly Diagram) I

The 7601 is mapped at Port 00 to 03 hexadecimal. To map the 7601 anywhere in the hexadecimal address range of OO-FF change the decoder outputs connected to SX and SY.

PORT ADDRESSES

Address lines AO and Al select one of four sequential port addresses. One input port and one output port reside at each address. The RD* and WR*

control inputs differentiate between input gating or output latch functions.

4. ADDRESS DECODER OPERATION

Refer to the schematic, Document #102783

The 7601 uses two cascaded 74LS42 decoders CU3, U4) to decode addres·s 1 i nes

A~-A7 . These decoders are enab 1 ed on I y when l'ORQi~ and I'OEXP* are act i ve.

Address lines AO, Al and the WR* signal are used to gate the select strobes which control the output ports) from u6. Address lines AO, Al and the RD*

signal are used to gate the select strobes' (which control the inptlt ports) from US.

CHANGING THE 7601 PORT ADDRESS

Refer to the assembly diagram, Document #102784

Locate decoders U3 and u4 (74LS42) adjacent to the STD BUS edge connector.

Each decoder device has a dual gow of pads which form decoder output select matrices. Make one (and only one) connection to each of the matrices adjacent

to U3 and U4.

The decoder jumper pads numbered as shown in the card address selection figure are adjacent to the decoder chips on the 7601. Also shown are the jumpers (at XO and YO) which produce hexadecimal port addresses 00, 01, 02, and 03, the selections made when the card is shipped.

YO QOOOOOOO Y1 ooooOQOO SY

FIGURE 3 - CARD ADDRESS SELECTION

PRO-LOG CORPORATION A

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FORM NO. 101905

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The I/O address mapping and jumper selection table for four addresses per card shows where to place jumpet straps to obtain any four sequential port addresses in the hexadecimal range OO-FF. Using the lower of the 2-digit hexadecimal addresses desired, find the most significant hexadecimal address digit along the vertical axis, and the least significant hex digit on the horizontal axis. For example, port addresses 50, 51, 52 and 53 are obtained by connecting jumpers at X2 and

v4.

The only restriction that applies in address selection for the 7601 is that the lower of the four port addresses (00 as shipped) must occur only at every

fourth possible address; for ex~mple, the sequence 01, 02, 03 and 04 is not allowed by the decoder.

The pad matrices adjacent to U3 and U'4 are on 0.10 inch (0.25cm) centers.

The jumper wires may be conveniently replaced by wirewrap post if frequent address selection changes are anticipated.

MOST I.EAST SIGNIFICANT HEX ADDRESS JUMPER

SIGNIFICANT

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HEX ADDRESS

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2 Xl yo 'Xl Yl Xl Y2 'Xl Y3

3 Xl y4 Xl Y5 Xl Y6 Xl Y7

4 X2 yo X2 Yl X2 Y2 X2 Y3

5 X2 Y4 X2 Y5 X2 Y6 X2 Y7

S X3 yo X3 Yl X3 Y2 X3 Y3 X

1 X3 Y4 X3 Y5 X3 v6 XJ Y7

a ^X4 vo X4 Yl X4 V2 X4 Y3 ANO

9 X4 Y4 X4 Y5 X4 V6 X4 Y7 Y

A X5 yo X5 Yl X5 Y2 X5 Y3

B X5 Y4 X5 Y5 X5 Y8 X5 V7

C X6 YO X6 Yl X6 Y2 X6 Y3

0 X6 Y4 X6 Y5 X6 Y6 X6 Y7

E X7 yo X7 Yl X7 Y2 X7 Y3

F x7 Y4 X7 Y5 X7 Y6 X7 Y7 /

FIGURE 4

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I/O Address Mapping And Jumper Selection Table For 4 Addresses Per Card

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CARD ENVIRONMENTAL SPECIFICATIONS

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6. ELECTRICAL SPECIFICATIONS

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7601 GENERAL PURPOSE TTL I/O CARD ELECTRtCAL TEST SPECIFtCATION

RECOMMENCED OPERATING LIMITS A8S0LUTE NON-OPERATING LIMITS

MNEM. PARAMETER

MIN. TYP. MAX. MIN. MAX. UNIT

Vee Supply voltage 4.75 5.00 5.25 0.0 700 Volt

TA Free air temp. 0 25 55 -40 75 C

USER WORST CASE ELECTRtCAL CHARACTERISTICS OVER RECOMMENDED TEST LIMITS

FOR AN INPUT PORT

MNEM PARAMETER MtN TVP MAX UNIT

V1H High Level Input Vo 1 tage 2.0 volt

VIL Low Level Input Voltage 0.7 volt

Hysteresi~.(V~+ ,- V_{T_)} 0.2 0.4 yol t

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FOR AN OUTPUT PORT

MNEM P.A.~..A.METER MIN TYP MAX UNIT

VOH High Level Output Vo I tage

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VOL Low level Output Voltage

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Each output can drive 20 LSTTL ^loads~':

STD BUS ELECTRICAL CHARACTERISTICS OVER RECOMMENDED TEST LIMITS

>-1NEM PARAMETER MIN TYP MAX UNIT

ICC Supply Current 300 475 mA

STO BUS tnput Load See Figure 6 STD BUS OutDut Drive See Figure 6

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7.

MECHANICAL

• Meets aU STD BUS general mechanical specifi- cations

• May require one additional card slot width (O.S inch) for ribbon cable access to port sockets.

• Connectors use low profile 1S-pin DIP plugs with heavy duty pins. T and 8 Ansley catalog No.

609-M16SH or equivalent

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FORM NO. 101905

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STO/71101 EDGE CONNECTOR PIN LIST PIN NUMBER PIN NUMBER

OUTPUT (DAIVE) OUTPUT (DRIVEl

INPUT (LOADING)** INPUT (LOADING) ,':7' ..

MNEMONIC MNEMONIC

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A14 18 17 1 A6

A13 20 '9 1 A5

A12 22 21 1 A4

All 24 23 1 A3

Al0 26 25 1 A2

A9 28 27 2 AI

A8 30 29 2 AO

RO' 1 32 31 1 WR'

MEMRO' 34 33 1 lORa'

MEMEX' 36 35 1 10EXP'

MCSYNC' 38 37 REFRES~'

STATUS O' .10 39 STATUS "

BUSRO' .12 .1\1 BUSAK'

INTRa' .14 .lJ INTAK'

NMIRO' 46 45 WAITRQ'

P8F1ESET' 48 47 1 ' SYSFIESET"

CNTFII.' 50 .l9 CLOCK'

PCI IN 52 51 our PCO

AUX. GNO 54 53 AUX GNO

AUX .1/ 56 55 AUX ·oJ

'O"ICJft.t" Actlv. Low L.., .. LoqlC

1:1: Designates LSTTL Loads

FIGURE 6

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Edge Connector Ptn List

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0 - 1 16 I -

1 - 2 15 ~

2 - 3 14 f--4

3 - 4 13

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4 - 5 12H.

5 - 6 11 H.

6 - 7 10 H~

7 - 8

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Input or Output Port Socket

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FORM NO. 101905

B.

7601 OPERATING SUBROUTINE MODULES

This section provides flow diagrams and subroutines- to operate your 7601 card. These may be used intact, or used as models to construct subroutines for a specific application.

The subroutines are written in B080-family assembly code and will execute on 8080. 8085, and z80 processors. The memory addresses selected are compatible with Pro-Log's 7801 (808SA) and 7803 (Z80) processor cards!

The 7601 port addresses used are the address jumper selections made when the 7601 is shipped.

To use these subroutines in systems other than those described above, the memory andlor 1/0 port addresses may req~ire change for compatibility!

The flow diagrams presented can be easily translated into the assembly code used by any microprocessor since th~y show the steps required to achieve 7601 operation without reference to a particular microprocessor.

The (Check Bits) subroutine will compare the present input port status with the port status from the last time that the port was read.

To use the routine the HL pointer must point to a place in memory where port status is stored. Also the port must be read into the Accumulator before calling the routine.

Upon return from the routine the location that the HL pointer was previously set will contain new port status. Plus the next four locations will contain change status.

Uses Reg is ters A, Hand L

M XX New Data ~ Location HL was set to M + 1 XX Old Data

M + 2 ^{XX Changes} M + 1 XX Bit,s to Zero

M +

4 xx

Bits to One Memory after Return

The (Set Bit) routine can set a bit or bits on an output port. To use the routine, load the accumulator with the bits that should be changed and set the HL pointer to a place in memory where the port status is stored.

The (Clear Bit) routine can clear a bit or bits on an output port. To use the routine, load the accumulator with the bits that should be changed and set the HL poJnter to a place in memory where the port status is stored.

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FORM NO, 101905

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LOAD B WITH OLD DATA EXCLUSIVE "OR"

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STORE BITS THAT

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RESl'ORE B & C

RETURN

CORPORATION

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