pure COLD: working principle
0.0 0.1 0.2 0.3 0.4 0.5 0.6
-1.5µ -1.0µ -500.0n 0.0 500.0n 1.0µ 1.5µ 2.0µ 2.5µ 0.00
0.50 1.00 1.50 2.00 2.50
α-branch signal [ V ]
α-branch
timing signal [ V ]
time [ s ]
timing signal
pile up rejection electronics for Cryo On-Line Detectors
(heavy elements chemistry)
β α pile up signals can reliably be
measured in the „timing channel“ only
pureCOLD: Comparator / ADC / FPGA stages
16 × fast comparators per timing channel
• 150 ps delay, 10ps jitter
• run-time matching via cable delay better 0.7 ps
• levels adjustable via DAC
8 phase sampling clock
• derived from a 250 MHz low jitter clock generator
• run-time matching via
“cable” delay better 0.3 ps
• time resolution 0.5 ns
2 × 500 kSamples/s ADC per spectr. channel
• 16 bit conversion depth
• 2.5 V bipolar range
• 120 ns conversion time
• 1.8 µs serial read-out time
Spartan 3 FPGA
• 340 event FIFO
• 110 µs serial transfer to MB
• max. rate 9 kevents per sec
• time between consecutive events 4 µs
• 7x free programmable interconnection signals
pureCOLD: missing event rate
100 101 102 103 104 105
10-4 10-3 10-2 10-1 100 101 102 103 104 105
old DAQ pureCOLD ADC limit
lost rate [1/s]
event rate [1/s]
dead time 4 µs dead time
250 µs
1000 events/s
dead time 2 µs 220 events/s
0.144 events/s
major achievements:
- S/N optimized
- dead time / event minimized
- over all remote control implemented
pureCOLD: typ. signals
0.0 500.0n 1.0µ 1.5µ 2.0µ 2.5µ 3.0µ 3.5µ 0.0
0.5 1.0 1.5 2.0 2.5
amplitude [ V ]
time [ s ]
timing-branch α-branch
-2.5µ -2.0µ -1.5µ -1.0µ -500.0n 0.0 500.0n 1.0µ 0.0
0.5 1.0 1.5 2.0 2.5
amplitude [ V ]
time [ s ]
timing-branch α-branch
232 U - test-spectrum
4 6 8 10 12 14
100 101 102 103 104 105 106 107
224 Ra212 Bi220 Rn 216 Po 212 Po (34 ps)
212g Po
232 U228 Th
232U on PIN-diode 19.4 Mio events FWHM = 100 keV
counts per 25 keV
energy [ MeV ]
232 U
