Strip Technology and HVMPAS

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Strip Technology and HVMPAS

Ivan Perić for HVCMOS collaboration*

HVCMOS collaboration:

Bonn:

Malte Backhaus, Tomasz Hemperek, Fabian Hügging, Hans Krüger CERN:

Lingxin Meng, Daniel Münstermann CPPM:

Marlon Barbero, Frederic Bompard, Patrick Breugnon, Jean-Claude Clemens, Denis Fougeron, Patrick Pangaud, Alexandre Rozanov

LBNL:

Maurice Garcia-Sciveres Heodelberg:

Christan Kreidl, Ivan Perić

(2)

Vertex 2012, Ivan Peric

Overview

• High-Voltage CMOS Sensors - introduction

• Summary of the old results

• High-Voltage CMOS Sensors for ATLAS

(3)

High-voltage CMOS pixel detectors

or “smart diode arrays”

(4)

HV CMOS detectors

• The distinguishable property of HV CMOS sensors is that the CMOS pixel electronics is placed inside the sensor diode.

• This allows:

• 1) Construction of pixel arrays without insensitive regions.

• 2) High reverse biasing of the sensor diodes.

• 3) Fast charge collection based on drift.

(5)

HV CMOS detectors

• We start with a low voltage process:

• PMOS and NMOS transistors are placed inside their shallow wells.

PMOS NMOS

Shallow n-well

Shallow p-well

(6)

HV CMOS detectors

• A deep n-well surrounds the electronics of every pixel.

PMOS NMOS

deep n-well

(7)

HV CMOS detectors

• The deep n-wells isolate the pixel electronics from the p-type substrate.

PMOS NMOS

deep n-well

p-substrate

(8)

HV CMOS detectors

• Since the pixel-transistors do not “see” the substrate potential, the substrate can be biased low without damaging the transistors.

• In this way the depletion zones in the volume around the n-wells are formed.

• => Potential minima for electrons

PMOS NMOS

p-substrate

Depletion zone

Potential energy (e-) deep n-well

(9)

HV CMOS detectors

• Since the pixel-transistors do not “see” the substrate potential, the substrate can be biased low without damaging the transistors.

• In this way the depletion zones in the volume around the n-wells are formed.

• => Potential minima for electrons

• Charge collection occurs by drift

PMOS NMOS

p-substrate

Depletion zone

Drift

(10)

HV CMOS detectors

• Collected charge causes a voltage change in the n-well.

• This signal is sensed by the amplifier – placed in the n-well.

PMOS

N-well

NMOS

D S

G

holes electrons

P-well P-substrate

(11)

HV CMOS detectors

• Collected charge causes a voltage change in the n-well.

• This signal is sensed by the amplifier – placed in the n-well.

P-substrate

(12)

HV CMOS detectors

P-substrate

• Collected charge causes a voltage change in the n-well.

• This signal is sensed by the amplifier – placed in the n-well.

(13)

HV CMOS detectors

• Maximizing of the depleted regions improves performances (less capacitance and noise, more signal) – the best results can be achieved in high-voltage technologies.

PMOS NMOS

p-substrate

Depletion zone

(14)

HV CMOS detectors

• Example AMS 350nm HVCMOS: Typical reverse bias voltage is 60 V and the depleted region depth ~15 m.

PMOS NMOS

Depletion zone

60V ~15µm

deep n-well

(15)

HV CMOS detectors

• Example AMS 350nm HVCMOS: Typical reverse bias voltage is 60 V and the depleted region depth ~15 m.

• 20cm substrate resistance -> acceptor density ~ 10

¹⁵

cm

^-3

PMOS NMOS

Depletion zone

60V ~15µm

deep n-well

(16)

HV CMOS detectors

• Since the sensor diodes are equipped with electronics we call them “smart” and the structure

“smart diode array”.

• The structure can be designed also in LV processes that have a deep n-well that surrounds both types of shallow wells entirely.

• An example of such a LV technology is UMC 180nm.

PMOS NMOS

Depletion zone

60V ~15µm

deep n-well

Smart diode

(17)

CMOS pixel flavors

• CMOS pixel flavors:

Standard MAPS INMAPS

„HVMAPS“ – HVCMOS or SDA TWELL MAPS

(18)

A “smart diode” layout

40 µm

(19)

Layout example: intelligent diode

40 µm

(20)

20

Project results

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Project history

2006

„Proof of principle“ phase

1) Simple (4T) integrating pixels with pulsed reset and rolling shutter RO (Possible applications: ILC, transmission electron microscopy, etc.) 2) Pixels with complex CMOS-based pixel electronics

(Possible applications: CLIC, LHC, CBM, etc.)

3) CCPDs based on a pixel sensor implemented as a smart diode array 350nm AMS HV technology

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Project history

The type 1 chip HVPixelM:

Simple (4T) integrating pixels with pulsed reset and rolling shutter RO

21x21 µm pixel size

Efficiency at TB: ~98% (probably due to rolling shutter effects

Seed pixel SNR 27, seed signal 1200e, cluster 2000e

Spatial resolution 3-3.8µm

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Project history

0 500 1000 1500 2000

0.0 0.2 0.4 0.6 0.8 1.0

Efficiency

Signal [e]

Efficiency - window 800ns

CAPPIX/CAPSENSE edgeless CCPD 50x50 µm pixel size

Signals and noise of a CAPSENSE pixel after 10¹⁵n_eq/cm²

Detection efficiency vs. amplitude

(24)

New projects

180nm AMS HV technology

Applications:

1) Transmission electron microscopy integrating pixels with pulsed reset and rolling shutter RO – in-pixel CDS 2) Mu3e experiment at PSI

Monolithic CMOS pixels with CSA 3) ATLAS (and CLIC)

CCPDs based on smart sensors 65nm UMCLV technology

2006

„Proof of principle“ phase 350nm AMS HV technology

(25)

Technology issues – crosstalk

PSUB DN

PW NW or SN

1.8v

DP

1.8v PMOS NMOS

• Capacitive feedback into the sensor (n-well)

• Many important circuits do not cause problems: charge sensitive amplifier, simple shaper, tune DAC, SRAM but…

• “Active” (clocked) CMOS logic gates and sometimes comparators cause large crosstalk

• Possibility 1: Implement the circuits only using NMOST: effects on radiation tolerance, layout area, power consumption, etc.

• Possibility 2: Place the active digital circuits on the chip periphery or on separate chip.

• Possibility 3: Isolate PMOST from n-well using an additional standard technology feature – the

deep P-well – we still haven’t tested it…

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26 Sensor concepts

• Pixel electronics is based on a charge-sensitive amplifier and optionally a comparator.

• The pixel signal/address is sent as an analog information.

• The signal processed by the digital circuits are on the chip periphery or on a separate chip.

• 1) Mu3e: The pixel signal is processed on the sensor chip itself -> monolithic pixel detector.

• 2) ATLAS: intelligent sensor concept. The pixel address is transmitted to an existing readout chip, like FEI4 or an strip-readout chip.

Readout Electronics Pixels

Readout Electronics

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Time walk measurement

• The digital part accepts only the comparator signals that are within the trigger window.

• Time resolution tests possible.

• Time resolution is the sum of time walk and signal collection time.

Test signal

Ampl. out

Comp out Window

Test signal

Ampl. out

Comp out Window

del1

del2

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28 Time walk measurement

• In-time efficiency vs. signal amplitude (40ns time window).

• Detection of signals > 1230 e with 40ns time resolution possible.

• Power consumption of the pixel 7.5µm.

• We expect at least 1500 e from MIPs.

0 1000 2000 3000 4000 5000 6000

0.0 0.2 0.4 0.6 0.8 1.0

40ns window

Fit: Mean Val.: 732.20782 Sigma: 172.7808

Efficiency

Signal [e]

(29)

Collection time measurement

• Comparison of the response delay to capacitive test pulse (delay only caused by the amplifier) and the delay to IR pulse (delay caused by the amplifier and collection time).

• To assure that amplifier delay is equal, we equalize the signal amplitudes for both injections.

• The amplitudes are measured as ToT.

Test signal

Ampl. out

Comp out

IR laser signal Ampl. out

Comp out del2

1400e

N-well 5µ m

10µ m

60%

drift ToT is proportional to the input charge.

It does not depend on the amplifier rise times.

Absorption of 850nm light ~14µm

Similar spatial distribution of the charge generation as for MIPs

Depleted (drift)

40%

diffusion

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30 Collection time measurement

• Charge collection time – IR laser, comparison with the fast capacitive injection.

• No measurable delay versus the capacitive test pulse.

0.790 0.795 0.800 0.805 0.810

95 100 105 110 115 120 125 130 135 140 145

150 Test pulse

IR laser - 850nm

Delay [ns]

Threshold [V]

0 100 200 300 400 4000

0.78 0.79 0.80 0.81

0.82 Test pulse

IR laser - 850nm

Threshold[V]

Time[ns]

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High-Voltage CMOS Detectors for ATLAS

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32 High-Voltage CMOS Detectors for ATLAS/CLIC

• Smart sensor concept

• We use one of the existing RO chips for the readout of a HVCMOS sensor.

• This approach simplifies the design of sensor and allows us to use the existing

readout- and data-acquisition-systems.

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Strip-like Concept

(34)

34 Pixel detector compatible to strip-readout electronics

• The present LHC strip detectors consist of large-area strip sensors that are connected by wire bonds to multi-channel ASICs

• We use the strip readout ASIC for the readout of our SDA sensor

Comparator or ADC

Readout ASIC (such as ABCN) Strip sensor

Strip CSA

Wire-bonds

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Pixel detector compatible to strip-readout electronics

• We replace a strip with a line („gang“) of pixels

Comparator or ADC

Readout ASIC (such as ABCN) Pixels CMOS sensor

CSA

Wire-bonds

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36 Pixel detector compatible to strip-readout electronics

• Every pixel generates a digital current pulse with unique amplitude

• The pixel outputs are summed, converted to voltage signal and transmitted to readout ASIC by capacitive coupling

Comparator or ADC

CSA

Wire-bonds

Summing line

(37)

Pixel detector compatible to strip-readout electronics

• The pixel address is transmitted as analog information

Comparator or ADC

CSA

Wire-bonds

Summing line

(38)

38 Simultaneous readout from two 2D sensitive layers

• Simultaneous readout from two 2D sensitive layers. Signals from two sensor layers can be easily combined in a single readout ASIC

Comparator or ADC CSA

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Pixel detector compatible to strip-readout electronics

• A large area CMOS sensor can be produced by stitching several 2cm x 2cm wafer reticles.

• Any arbitrary pixel group pattern is possible.

• Advantages:

• Commercial sensor technology – lower price per unit area.

• Intrinsic 2D spatial resolution (e.g. 25 m x 125 m binary resolution)

• No need for bias voltages higher than 60V.

• Operation at temperatures above 0C is according to tests possible (irradiations to 10

¹⁵

n

_eq

/cm

²

).

• Thinning possible.

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40

CCPD Concept

(41)

CCPD for ATLAS pixel detector

• We use one of the existing RO chips for the readout of an intelligent HVCMOS sensor.

• This approach simplifies the design of sensor and allows us to use the existing readout- and data- acquisition-systems.

• Intelligence: the pixels are able to distinguish a signal from the background and to respond to a particle hit by generating an address information.

Pixel readout chip (FE-chip)

Pixel sensor

Pixel length = 250 μm Bump-bond

Pixel electronics based on CSA Bump-bond pad

We replace the standard bump-bonded sensor with…

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42 CCPD for ATLAS pixel detector

• The HV CMOS sensor pixels are smaller than the standard ATLAS pixels, in our case 33μm x 125μm - so that three such pixels cover the area of the original pixel.

• The HV pixels contain low-power (~ 7μW) CMOS electronics based on a charge sensitive amplifier and a comparator.

Glue Pixel readout chip (FE-chip)

Pixel CMOS sensor 33x 125 μm

Summing line Transmitting

plate

Pixel electronics based on CSA

Bump-bond pad Coupling

capacitance

…the capacitive coupled HV CMOS sensor

(43)

CCPD for ATLAS pixel detector

• The electronics responds to a particle hit by generating a pulse.

• The signals of a few pixels are summed, converted to voltage and transmitted to the charge sensitive amplifier in the corresponding channel of the FE chip using AC coupling.

• Each of the pixels that couple to one FE receiver has its unique signal amplitude, so that the pixel can be identified by examining the amplitude information generated in FE chip.

• In this way, spatial resolution in - and z-direction can be improved.

Glue Pixel readout chip (FE-chip)

Pixel CMOS sensor 33x 125 μm

Summing line Transmitting

plate

Pixel electronics based on CSA

Bump-bond pad Coupling

capacitance

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44 Advantages compared to existing detectors

• No need for bump-bond connection between the sensor and readout chip – lower price, better mechanical stability, less material.

• Commercial technology – lower price.

• No need for bias voltages higher than 60V.

• Operation at temperatures above 0C is according to tests possible (irradiations to 10

¹⁵

n

_eq

/cm

²

).

• Increased spatial resolution (e.g. 25m x 125m binary resolution) with the existing FE chip

• Smaller clusters at high incidence angles.

• Possibility of sensor-thinning without signal loss. Since we do not use bumps and FE chips can be thinned as well, the amount of material would be very low.

• Interesting choice for other experiments where low-mass detectors are needed such as CLIC, ILC,

CBM, etc...

(45)

Module concept

Sensor

FE chip Sensor

FE chip

PCB Wire bonds for FE chips

Wire bonds for sensor

Module position in detector

(46)

46 Advantages compared to existing detectors

• No need for bump-bond connection between the sensor and readout chip – lower price, better mechanical stability, less material.

• Commercial sensor technology – lower price.

• No need for bias voltages higher than 60V.

• Operation at temperatures above 0C is according to tests possible (irradiations to 10

¹⁵

n

_eq

/cm

²

).

• Increased spatial resolution (e.g. 25m x 125m binary resolution) with the existing FE chip

• Smaller clusters at high incidence angles.

• Possibility of sensor-thinning without signal loss. Since we do not use bumps and FE chips can be thinned as well, the amount of material would be very low.

• Interesting choice for other experiments where low-mass detectors are needed such as CLIC, ILC,

CBM, etc...

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Test Chip HV2FEI4

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48 HV2FEI4

• Pixel matrix: 60x24 pixels

• Pixel size 33 m x 125 m

• 21 IO pads at the lower side for CCPD operation

• 40 strip-readout pads (100 m pitch) at the lower side and 22 IO pads at the upper side for strip-operation

• Pixel contains charge sensitive amplifier, comparator and tune DAC.

Strip pads

IO pads for CCPD operation

IO pads for strip operation

Pixel matrix

4.4mm

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HV2FEI4 - Architecture

Matrix

20x3

12x2

Column control

Strip Pads

Bias DACs

IO pads for CCPD operation IO pads for strip operation

Cap. Injection

Test Pad SFOut

(50)

50 Strip and Test-Operation

Bias A

Bias B

Bias C

Pad

125um

33um

SelectL=0 SelectR=0

L0 R0 L1 R1 L2 R2

Mon Pad

Column control SR

Row control SR 3 3

Strip bus

(51)

CCPD Operation

2

3

1

2

3

1

Bias A

Bias B

Bias C FEI4 Pixels

CCPD Pixels

Signal transmitted capacitively

(52)

52 Pixel electronics

A

D D

CCPD bus Strip bus 4-bit DAC

(CR filter)

Programmable current Select G

G

In<0:3> G RW

SFOut

Cap. Injection Amplifier

Filter

Comparator Output stage CCPD electrode

BL

Th

(53)

6 Pixels – Layout

Comparator

Amplifier Tune DAC

33 µm

(54)

54

Experimental results

(strip operation)

(55)

Strip-like operation

Strip like operation – ⁵⁵Fe signals – three pixel columns (each 24 pixels) readout in parallel The amplitude depends on pixel position

“Hit-bus” operation – ⁵⁵Fe signals – three pixel columns (each 24 pixels) readout in parallel The amplitude is set to be equal for every pixel

(56)

56 Strip-like operation

“Hit-bus” operation – ²²Na signals – one pixel columns (24 pixels) readout in parallel The amplitude is set to be equal for every pixel - values around 50mV

0.02 0.04 0.06 0.08

0 500 1000 1500 2000 2500 3000

Signal number

Amplidude [V]

22Na irradiation

-5.0µ 0.0 5.0µ 10.0µ 15.0µ 20.0µ

-0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.00 0.01

Amplitude [V]

Time [s]

“Hit-bus” operation – ²²Na signals – one pixel columns (24 pixels) readout in parallel The amplitude depends on pixel position

-5.0µ 0.0 5.0µ 10.0µ 15.0µ 20.0µ

-0.11 -0.10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.00 0.01

Amplitude [V]

Time [s]

(57)

Strip-like operation

0 5 10 15 20 25

0.045 0.050 0.055 0.060 0.065 0.070 0.075

Amplitude

Position in row

0.00 0.02 0.04 0.06 0.08

0 10 20 30 40 50 60

Number of signals

Amplitude [V]

Test injection

“Hit-bus” operation – test injection pulses (~ 1700e) The amplitude depends on pixel position

(58)

VDDA – VSSA – Threshold – Gate – HV

Irradiation area

The on-board LVDS chip runs to load the HV2FEI4 chip.

The Analog current-shaped "Monitor"

signal is read-back and amplified through an analog amplifier

RS232

DE2 board

The system allows to read by using the

MONITOR signal, and to write the HV2FEI4 chip

HV2FEI4 Board n°2 4 signals

0,4V max 5V max

Monitor signal 20m long cable 1,8V

5m

Monitor signal 3,3V

4 signals io

Lvds LVDS 20m long cable

Irradiation at PS (CERN)

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Results after 144 MRad

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60 Results after 144 MRad

0 20 40 60 80 100 120 140

0 20 40 60 80

AmpOut rate [part/spill]

HV [Volts]

Rate vs. HV

20 22 24 26 28 30 32 34 36 38 40

0 50 100 150 200

Temperature [C]

Power [mW]

Temperature vs. power

0 50 100 150 200 250 300 350 400

0 20 40 60 80

Current HV [uA]

Power [mW]

Leakage current vs. power (HV=30V)

0 100 200 300 400 500

0 10 20 30 40 50 60 70

Current HV [uA]

HV [Volts]

Leakage current vs. HV

(61)

Experimental results

(CCPD operation)

(62)

62 Measurement setup

(63)

Measurements with test pad

Injection HVCMOS

FEI4

Test pad

(64)

64 Measurements with test pad

0.577V -> 2964e =>

Capacitance = 0.824fF

0.50 0.52 0.54 0.56 0.58 0.60 0.62 0.0

0.2 0.4 0.6 0.8

1.0 Mean Val.: 0.57566 V Sigma: 0.01463 V

Response probability

Test pulse [V]

1550 1600 1650 1700 1750 1800 1850 1900 1950 0.0

0.2 0.4 0.6 0.8

1.0 Mean Val. 1745.0 e sig 73.0 e

Response probability

Injected charge [e]

Calibrated input: FEI4 noise 73e (FEI4 threshold was set to 1300e)

(65)

Measurements with active pixels and test injection

Injection HVCMOS

FEI4

Test pad

1700 1800 1900 2000 2100 2200 2300 0.0

0.2 0.4 0.6 0.8

1.0 Mean Val.: 1997.8 e sigma: 169.6 e

Number of Hits

Injected signal [e]

(66)

66 Measurements with Na22 beta source

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Conclusions

• We are investigating the use of HVCMOS technology for ATLAS detectors

• The concept: Intelligent sensors in HVCMOS technology readout by the existing readout ASCIs

• Advantages:

• Commercial sensor technology – lower price per unit area.

• No need for bias voltages higher than 60V.

• Operation at temperatures above 0C is according to tests possible (irradiations to 10

¹⁵

n

_eq

/cm

²

).

• Thinning possible.

• Test chip HV2FEI4 has been tested in the stand alone mode and as a CCPD readout with FEI4

• First measurements with a strip readout chips will be done soon.

• In stand alone mode, we measure good performances of the HVCMOS chip

• In CCPD mode, noise somewhat increased due to non optimal setup

• Irradiation ongoing, we have reached 180MRad so far, the detector still works – leakage current

increased (temperature: 38C).

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68

Thank you

(69)

Backup Slides

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70 Experimental results - overview

HVPixel1 – CMOS in-pixel electronics with hit detection Binary RO

Pixel size 55x55μm Noise 60e

MIP seed pixel signal 1800 e Time resolution 200ns

CCPD2 -capacitive coupled pixel detector Pixel size 50x50μm

Noise 30-40e Time resolution 300ns

MIP SNR 45-60

PM2 chip - frame mode readout Pixel size 21x21μm 4 PMOS pixel electronics

128 on-chip ADCs

Noise: 21e (lab) - 44e (test beam) MIP signal - cluster: 2000e/seed: 1200e Test beam: Detection efficiency >98%

Seed Pixel SNR ~ 27

Cluster signal/seed pixel noise ~ 47 Spatial resolution ~ 3.8 m Irradiations of test pixels

60MRad – MIP SNR 22 at 10C (CCPD1) 10¹⁵n_eq MIP SNR 50 at 10C (CCPD2)

Monolithic detector - frame readout Capacitive coupled hybrid detector

MuPixel –

Monolithic pixel sensor for Mu3e experiment at PSI Charge sensitive amplifier in

pixels

Hit detection, zero suppression and time measurement at chip

periphery

Pixel size: 39x30 μm (test chip) (80 x 80 μm required later) MIP seed signal 1500e (expected)

Noise: ~40 e (measured) Time resolution < 40ns

Power consumption 7.5µW/pixel HV2FEI4 chip (first test next week!!!)

CCPD for ATLAS pixel detector Readout with FEI4 chip Reduced pixel size: 33x125μm RO type: capacitive and strip like 3 pixels connected to one FEI channel

HPixel - frame mode readout In-pixel CMOS electronics with CDS

128 on-chip ADCs Pixel size 25x25 μm Noise:60-100e (preliminary) MIP signal - cluster: 2100e/seed: 1000e

(expected)

SDS - frame mode readout Pixel size 2.5x2.5 μm

4 PMOS electronics Noise: 20e (preliminary) MIP signal (~1000e - estimation) Monolithic detector –

continuous readout with time measurement

1. Technology 350nm HV – substrate 20 cm uniform 2. Technology 180nm HV – substrate 10 cm uniform 3. Technology 65nm LV – substrate 10 cm/10 m epi

(71)

Capacitively Coupled Pixel Detectors

CCPDs

(72)

72 Standard hybrid detector

Fully-depleted sensor Readout chip

Bumps Min. pitch ~50 μm

Pixel

Signal charge

Charge signal is transmitted

(73)

CCPD with a “passive” sensor

Fully-depleted sensor Readout chip

Min. pitch < 50 μm

Pixel

Signal charge

Signal ~30mV for 250µm thick sensor (Cdet = 100fF) Voltage signal is transmitted

Requires bias resistors on the sensor

Can be implemented as punch-through structure

(74)

74 Active CCPD

Smart diode- or fully-depleted sensor Readout chip

Pixel

Signal charge

Signal >30mV for very thin sensors

Sensor implemented as SDA Advantage:

Charge to voltage amplification on the sensor chip

Typical voltage signal ~100mV Easier capacitive transmission Can be thinned without signal loss