FEATURES
• TRANSPARENT ECC CORRECTION
• MULTl-SECTOR READlWRITE CAPABIUTY
• DMA OR PROGRAMMED 110 OPERATION the complexity of the interface design, device count, board SIZe reQuirements and increases system reliability.
The WD1014 operates from a single ... 5V supply and is available in a 40 pin plastic or ceramic Dual-in-une package.
PIN
NUMBER SYMBOL DESCRIPTION
1-8 DAI..7-O Data Access Lines. Commands, status, and data to and trom buffer are transferred over this tristate bidirectional data bus controlled by the host.
DAL.7 is MSB.
9 CS Chip Select must be active for all communications with the BMEC.
10 RE Read Enable. For reading data and status information from the BMEC.
11 WE Write Enable. For writing commands and data to the BMEC.
12 Ml=i Master Reset Initializes the BMEC and clears the status flags when ac·
tivated.
13-15 AQ.2 Address inputs. Used to select task file registers and data buffer. A2. A 1, AD
= 000 selects buffer. A2 is MSB.
16 INTRQ INTerrupt ReQuest Activated whenever a command has been completed. It is reset when the status register is read. or when a new command is lOaded via OAL.7-O.
17 ORO Data ReQuest Set whenever the buffer contains data to be read by the host or is awaiting data to be written by the host
18 CL.K Clock signal input used for all intemal timing.
19 HOS Head & Drive Select for setting HSQ.3 and 051-4.
20 Vss GROUND
21·23 XA2'() These address lines are used to address the disk controller when xes = O.
24 BCiNC Buffer Counter INCrement Increments the extemal buffer counter. Each negative transition is a one byte count
25 BBSY Buffer BuSY. Signals the BMEC that the buffer is being accessed by the disk controller. It is also used to control AOQ.7 bus switching and tristate
xwet
and ~ when it is active.26 BROY Butter ReaDY output Signals the disk controller when the buffer memory is ready for controller data transfers. It is active when the buffer memory is full or empty.
Z7 ALoE Address Latch Enable. Used to set the extemal butter address whenever the buffer is not being accessed by the W01010 processor.
28 ~ Ram Chip Select. Asserted when the BMEC or host accesses the extemal butter.
29 XRE Tristate line activated only when eBSY = high. When ~ is lOW, in-formation is read from the'selected W01010 task files registers.
When Res is low, data is read from the butter.
30 XWE Tristate line activated only when BBSY = high. When
xes
is low, command or task file information is written into the disk controlier.When ~ is low data is written into the butter.
31
xes
This Chip Select is used to access the disk controlier.32-39 A07'() Address or Data bus shared by the butter, BMEC and the W01010. While ALoE is active a new buffer address is latched in an extemal counter, where A07=A14 and AOO=A7. This allows buffer sizes from 128 bytes to 32K addressed by a multiplexed data/address bus (ACO-7),
which is also shared by the WD1010 and drive/head control latches. The WD1014 manages the extemal sector buffer so that it can sUp;lort all W01010 sector sizes in singl~ and multiple sector operations. All buffer control signals required by the W01010 are produced by the BMEC so that no external logic is required to interface the W01010 to the BMEC.
During sector reads and writes. the BMEC produces an Error Correction Code (ECG) as data is transferred to and from the buffer. The user may select either a 32 or 56 bit polynomial depending upon his needs.
Errors are detected and corrected without in-tervention by the host. The BMEC controls all retries on data ECC errors for the host as well. Corrected errors are reported as a status to the host. Un-correctable errors are reported by setting the error bit in the status register with the appropriate descriptor bit set in the error register.
TASK FtLE 1 ISector Number Sector Number
o ICYlinder Number Cylinder Number
(low) (low)
1 iCylinder Number Cylinder Number
(high) (high)
SO H' SO H'
·S D H bytes specifies sector size. drive number and head number.
The SOH register is coded as follows:
Bit 7 (MSB) is set for a 7 byte sector extension (used
register. Command execution starts immediately after the command register is loaded and sub-sequent register loads are ignored until the corn-mand is done. The comcorn-mands are as follows:
BIT CODe
0=0: Interrupt for programmed I/O mode M
=
1: Multiple Sector Read or Write THE STATUS AND ERROR REGISTERSThe Status Register indicates to the host the status of the system. If the Error bit in the Status Register IS
set. one or more bits in the Error Register will be set.
The meaning of the these bits IS shown below:
6
COMMAND command is echoed. Stepping rate (RO-R3) is set Passes command to W01010 which scans 10 headers on cunent track. Updates cylinder number in task file and
I
command and initiates a read status after the command I
is completed. The command is echoed.
Write the buffer with data from W01010. If ECC is
I
The Write Long command' functions similarly to the Write Sector command except the ECC operation of computing the ECC word is inhibited in the BMEC. Instead. the BMEC accepts a 32, or 56 bit appendage from the host and passes it IJnaltered to the W01010 to be written on the disc after the data.
COMMAND FORMAT DESCRIPTION
READ COPY 10100MOE The Read Copy command is similar to the Read Sector command. except the BMEC does not send a data request (ORO) to the host at the end of the command.
This command, when used with the Write Copy com-mand, allows the copying of data from one disk to another with minimal host intervention.
SET PARAMETERS 11010000 The buffer size parameter is specified by the value held in the sector size task register. The buffer size corresponds to the sector Size task register value multiplied by 128.
j (E.G. if the sector size task register value = '. then it speci·
I fies a buffer size of 128 bytes. A 32768 (321<) byte length I I buffer is specified by a sector size register value = 0.)
A00-7
II
RCS
W01014 BMEC
ALE W01010
Wlncnnter DRIVE
Contnllier INTERFACE
OAL.
0·7 CS
HOST CS
m
REIFe ~ ~
wr AO
~ XAI AI
XA2 A2
AO BBSY BCS
A1 BRoy BRoy
A2 INTRa ORO
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