Edge connector P2 in Figure 3-2 is the VL-Bus connector. All bus master mode data transfers, including mailboxes, eCBs, and SCSI peripheral data are performed via the 32-bit VL-Bus. The DMA control logic on the VL-Bus host adapter controls the VL-Bus arbitration and data transfer operations. During DMA data transfers, the VL-Bus host adapter takes control of the VL-Bus and transfers data directly to and from the host memory. Both odd and even starting addresses are supported in the DMAlogic.
VL-Bus Pin Assignments
Table 3-6 summarizes pin asSignments for the VL-Bus connectors on the compo-nent side. Table 3-7 shows pin assignments on the solder side of P2B, a 116-pin edge connector.
3-8 • Part 3: VL-Bus Host Adapters
Table 3-6. Component Side Of P2A, Edge Connector
Signal Pln# Signal Name Direction
A1 DAT01 I/O
A2 DAT03 I/O
A3 GND Ground
A4 DAT05 I/O
A5 DAT07 I/O
A6 DAT09 I/O
A7 DAT11 I/O
A8 DAT13 110
A9 DAT15 I/O
A10 GND Ground
A11 DAT17 I/O
A12 Vee Power
A13 DAT19 I/O
A14 DAT21 I/O
A15 DAT23 I/O
A16 DAT25 110
A17 GND Ground
A18 DAT27 1/0
A19 DAT29 1/0
A20 DAT31 I/O
A21 ADR30 Output
A22 ADR28 Output
A23 ADR26 Output
A24 GND Ground
A25 ADR24 Output
A26 ADR22 Output
A27 Vee Power
A28 ADR20 Output
A29 ADR18 Output
A30 ADR16 Output
A31 ADR14 Output
A32 ADR12 Output
A33 ADR10 Output
A34 ADR08 Output
A35 GND Ground
A36 ADR06 Output
A37 ADR04 Output
A38 -WBACK Not used
Table 3-6. Component Side Of P2A, Edge Connector (Continued)
Signal Pint Signal Name Direction
A39 -BEO Output
A40 Vee Power
A41 -BE1 Output
A42 -BE2 Output
A43 GND Ground
A44 -BE3 Output
A45 -ADS Output
A46 Key Key
A47 Key Key
A48 -LRDY Output
A49 -LDEV<x> Not used
A50 -LREQ<x> Output
A51 GND Ground
A52 -LGNT<x> Input
A53 V cc Power
A54 ID2 Not used
A55 ID3 Not used
A56 ID4 Not used
A57 -LKEN Not used
A58 -LEADS Output
Table 3-7. Solder Side Of P2B, Edge Connector
Signal Pin # Signal Name Direction
B1 DATOO I/O
B2 DAT02 I/O
B3 DAT04 110
84 DAT06 110
85 DATOS I/O
86 GND Ground
87 DAT10 110
88 DAT12 I/O
89 V co Power
810 DAT14 I/O
811 DAT16 I/O
812 DAT18 I/O
813 DAT20 I/O
814 GND Ground
3-10. Part 3: VL-Bus HostAdapters
Table 3-7. Solder Side Of P2B, Edge Connector (Continued)
Signal Pint Signal Name Direction
B15 DAT22 1/0
B16 DAT24 1/0
B17 DAT26 1/0
B18 DAT28 1/0
B19 DAT30 1/0
B20 V co Power
B21 ADR31 Output
B22 GND Ground
B23 ADR29 Output
B24 ADR27 Output
B25 ADR25 Output
B26 ADR23 Output
B27 ADR21 Output
B28 ADR19 Output
B29 GND Ground
B30 ADR17 Output
B31 ADR15 Output
B32 Vee Power
B33 ADR13 Output
B34 ADR11 Output
B35 ADR09 Output
B36 ADR07 Output
B37 ADR05 Output
B38 GND Ground
B39 ADR03 Ouput
B40 ADR02 Output
B41 NC Not used
B42 -RESET Not used
B43 -D/C Output
B44 -MilO Output
B45 -W/R Output
B46 Key Key
B47 Key Key
B48 -RDYRTN Input
B49 GND Ground
B50 IRQ9 Not used
B51 -BRDY Input
B52 -BLAST Output
Table 3·7. Solder Side Of P2Bi Edge Connector (Continued)
P3 VL-Bus Signal Descriptions
The following is a description of the VL-Bus signals. All signal lines are TIL-com-patible. Signals preceded by a hyphen (-) indicate an active low signal.
Table 3·8. P3 VL·Bus Signal Descriptions
Signal Definition
ADR02-ADR31 Address Bus: The address bus furnishes the physical memory or 1/0 port addresses to the VL-Bus target. On the motherboard, these positive true signals can either directly connect to the CPU address bus, or be tri-state buffered. They are driven by the CPU for all CPU-initiated transfers.
During system I/O bus master or DMAcycies the VL-Bus controller drives system 1/0 bus addresses back to these signals. During VL-Bus master cycles, the VL-Bus device acting as bus master drives the address bus. If no VL-Bus target claims the transfer, the VL-Bus controller will drive the
VL~Bus master address to the system 1/0 bus.
·ADS
·BEO-·BE3
·BLAST
3-12 • Part 3: VL-Bus Host Adapters
Address Data Strobe: On the motherboard, this active low signal can ei-ther be directly connected to the CPU Address Data Strobe (-ADS) signal, or be tri-state buffered. During ISA DMAor ISA bus master transfers the VL-Bus controller acts as the active host on behalf on the ISA bus. This sig-nal is asserted by the VL-Bus conttoller for one clock cycle after the ad-dress bus and status lines are valid on the VL-Bus. During VL-Bus master transfers this signal is asserted by the active VL-Bus master for one clock cycle after the address bus and status lines are valid.
Byte Enables: The byte enables indicate which byte lanes of the 32-bit data bus are involved with the current VL-Bus transfer. On the mother-board, these active low signals can either be directly connected to the CPU Byte Enables (-BED -BE3) signal, or tri-state buffered. A 386SX class host CPU must translate AO, A 1, and -BHE to the proper byte enable format be-fore driving the Byte Enables (-BED - -BE3) signal to the VL-Bus targets.
The Byte Enables (-BEO - -BE3) signal is driven by the CPU for all CPU-initiated transfers. During system I/O bus master or DMA cycles the VL-Bus controller drives these signals according to the values of the system 1/
o
bus address lines 0, 1 and -SBHE. During VL-Bus master transfers the VL-Bus device acting as bus master drives -BEO through -BE3 to indicate which byte lanes contain valid data.Burst Last: This active low signal indicates that the next time the Burst Ready (-BRDY) signal is asserted the burst cycle will complete. On the motherboard this signal can either be directly connected to the CPU Burst Last (-BLAST) signal, or tri-state buffered. The 386SX and OX class host CPU must drive this signal low whenever the host controls the VL-Bus.
During VL-Bus master transfers the VL-Bus device acting as bus master drives this signal. A VL-Bus master that does not support burst transfers must drive this signal low whenever it controls the VL-Bus.
Table 3-8. P3 VL-Bus Signal Descriptions (Continued)
Signal Definition
-BRDY Burst Ready: This active low signal terminates the current active burst cycle. It is asserted low for one Local CPU Clock (LCLK) period at the end of each burst transfer. It must be synchronized to LCLK so that appropriate set up and hold times to LCLK are satisfied. If the Local Ready (-LRDY) signal is asserted at the same time as this signal, -BRDY is ignored and the remainder of the current burst cycle falls back to non-burst cycles. If a VL-Bus target does not support burst cycles, this signal can remain uncon-nected. This signal should not be asserted if the requesting device does not support burst transfers (Le., the Burst Last (-BLAST) signal is low).
DATOO-DAT31
-D/C
IDO-1D3
Tri-state control of this signal follows the same rules as the Local Ready (-LRDY) signal. It is shared among all VL-Bus devices; therefore, the active VL-Bus target drives it only during a burst transfer that it has claimed as its own. It must not be driven while the Address Data Strobe (-ADS) signal is asserted. Due to this restriction, the first cycle of a burst transfer must con-tain a minimum of one wait state. The active LBT must drive this signal high for one half LCLK cycle before tri-stating the sig nal. In most cases, this sig-nal should not be driven during the first T2 period because the system cache controller may be driving it. However, if the High Speed Write con-figuration bit is set, the LBT may start driving this signal during the first T2 state. While no burst cycle is active on the VL-Bus, this signal is held high by a 20K pull-up resistor located on the motherboard.
Data Bus: This is a bidirectional data path between VL-Bus devices and the CPU. On the motherboard the Data Bus (DATOO-DAT31) can either be directly connected to the CPU data bus or buffered. During read trans-fers the active VL-Bus target drives data onto the data bus. If the read is initiated from a system 1/0 bus master or motherboard DMA, the data is driven onto the system 1/0 bus data bus by the VL-Bus controller.
During write transfers the CPU, DMA slave, or bus master drives data onto the data bus. The Byte Enables (-BEO - -BE3) signal determines which byte lane(s) of the data bus (DATOO-DAT31) are valid.
Data or Code Status: The Data or Code Status (-D/C) signal indicates whether the current cycle is transferring data or code. This signal is useful to devices employing separate data and code caches. On the mother-board, the -D/C signal can either be directly connected to the CPU -D/C signal, or be tri-state buffered. During VL-Bus master transfers the VL-Bus device acting as bus master drives this signal. It the VL-Bus master does not differentiate between data and code, it must drive this signal to the de-fault data state (high) whenever it owns the VL-Bus.
Identifier Pins: The identifier (ID) pins allow any VL-Bus target to identify the type and speed of the host CPU. The ID pins typically are static levels and do not change values while the system is in operation; however, the ID pins are defined as valid only during power on reset (Le., while the Re-set (-RESET) signal is asserted and should be latched at the trailing edge of -RESET.
CPU Type ID<1> ID<O>
Reserved 0 0
386 0 1
486 1 0
Reserved 1 1
High Speed Write ID<2>
o
wait write minimum 1 1 wait write minimum 0 CPU Speed ID<3><=33 MHz 1
>33 MHz 0
Table 3-8. P3 VL-Bus Signal Descriptions (Continued)
ID<4> is reserved for future use and must always be set to zero.
The CPU Type Identifier bits describe the host CPU type. "386" describes a 386SX, 386DX, or compatible processor. "486" describes a 486SX, 486DX, 486D)(2, or compatible processor.
The High Speed Write Identifier bit is set if the VL -Bus controller is capable of handling high-speed zero wait state write transfers. Many motherboards with cache drive the CPU Ready(-RDY) and Burst Ready (-BRDY) signals during the first T2 state. Because the motherboard cache and the VL-Bus controller cannot simultaneously drive the CPU -RDY signal, the VL-Bus controller must wait until the second T2 when the cache is no longer driving the CPU RDY and BRDY signals. If a cache does not drive the CPU -RDYand -BRDY signals during the first T2 state, the High Speed Write bit is set because the VL-Bus controller may complete a write transfer with zero wait states. If the VL-Bus target cannot complete a write in zero wait states it may ignore this bit and default to a minimum of one wait states.
Read transfers are unaffected by the High Speed Write configuration bit setting.
The CPU Speed Identifier describes the maximum clock speed of the CPU. In the case of systems that can dynamically change the CPU speed (e.g., portables), the speed is defined as the maximum speed of the CPU.
A system with a clock speed of 33.3 MHz is considered 33 MHz.
,Interrupt Request Line 9: The IRQ9 Signal is a high-asserted, level-trig-gered interrupt that is electrically connected to the IRQ9 signal on the ISA bus. It is present on the VL-Bus connector for "standalone" VL-Bus device boards that do not have any system 1/0 bus signals available. Normally, the VL-Bus device should connect to the interrupt lines on the system VO bus. For Micro Channel systems, this signal is connected to the Micro Channel -IRQ 09 through an inverter on the motherboard.
Local Bus Size 16: This active low signal forces the CPU or LBM to run multiple 16-bit transfers to a VL-Bus target that cannot accept 32 bits of data in a single clock cycle. This signal is shared among all VL-Bus targets and must only be asserted by the active VL-Bus target. It must be asserted one clock cycle before the Local Ready (-LRDY) signal and must be held until the Ready Return (-RDYRTN) signal is sampled as active. It is then driven high one clock period before being released. While the VL-Bus is inactive, this signal is held high by a 20K pull-up resistor located on the
motherboard. '
Local CPU Clock: This signal is a 1 x clock that follows the same phase as a 486-type CPU. It is always driven by the system logic or by the VL-Bus controller to all VL-VL-Bus masters and targets. Its frequency range is up to 66 MHz. It is allowed to dynamically change frequencies if the system logic supports a dynamically changing clock. In the case of a 386 or other CPUs that use a clock running a 2x, the main clock must be divided down to a 1 x cloek. The rising edge of the clock signifies the change of CPU states.
Local Device: This signal is output by the VL-Bus target and signals the VL-Bus controller that the current cycle is a VL-Bus cycle. Each slot or de-vice has its own Local Dede-vice (-LDEV) signal associated with that slot or device. The VL-Bus controller samples this signal on the rising edge of the Local CPU Clock (LCLK) signal one cycle after -ADS or two LCLK cycles after -ADS. If the system I/O bus controller detects -LDEV<x> asserted, the current cycle does not start a system 1/0 bus cycle. The VL-Bus con-troller may optionally start a VL-Bus transfer even before sampling-LDEV <X> asserted if it knows a cycle is owned by a LBT (for example via registers intern to the VL-Bus controller). For cache-hit and system DRAM cycles, -LDEV is ignored. Because there is one -LDEV <X> signal per slot, all VL-Bus devices must drive -LDEV<x> to valid TIL levels at all times.
Table 3-8. P3 VL-Bus Signal Descriptions (Continued)
Local External Address Data Strobe: The VL-Bus controller or active VL-Bus master asserts this signal whenever an address is present on the VL-Bus that performs a CPU cache invalidation cycle. A VL-Bus master must drive this signal while it owns the bus. A VL-Bus master with an inter-nal cache may use this siginter-nal to invalidate its cache. This siginter-nal is not ac-tive for CPU writes, but the LBM can use the Address Data Strobe (-ADS) signal to invalidate CPU write transfers.
Local Bus Grant: This signal is used in conjunction with the Local Re-quest (-LREQ<x» signal to establish a VL-Bus bus arbitration protocol.
When the VL-Bus device asserts -LREQ<x>, the VL-Bus controller re-sponds by asserting the Local Bus Grant (-LGNT <x» signal for that slot.
The active VL -Bus master then has control of the VL -Bus and may own the bus until it no longer needs the bus or the VLBus controller removes -LGNT <X> to preempt the active VL-Bus master. There is one pair of-LREQ and -LGNT signals per slot.
Local Cache Enable: This active low signal is asserted if the current VL-Bus transfer is cacheable. It is always driver by the VL-VL-Bus controller. If it is asserted one clock before -LRDY and held until -RDYRTN is asserted during the last read in a cache line, the line is placed in the CPU cache.
The system designer must determine how the VL-Bus controller decides which transfers are cacheable.
Local Ready: This active low signal begins the handshake that termi-nates the current active bus cycle. It is shared among all VL-Bus devices.
The active LBT drives this signal only during the time of the cycle that it has claimed as its own. While the VL-Bus is inactive, this signal is held high by a 20K pull-up resistor located on the motherboard. Because the VL-Bus is normally a not-ready bus, the CPU must wait until this signal is asserted low to terminate an active VL-Bus cycle. This signal must be asserted low for one LCLK period. It is then driven high one clock period before being released. It is synchronized to LCLK so appropriate setup and hold times to LCLK must be satisfied. In most cases, -LRDY should not be driven the first T2 period because the system cache controller may be driving it. How-ever, if the High Speed Write configuration bit is set the LBT may start driv-ing this signal durdriv-ing the first T2 state.
Local Request: This active low signal is used in conjunction with the Local Bus Grant (-LGNT <X» signal. It is used by a VL-Bus device to gain control of the VL-Bus and become an active LBM. There is one pair of -LREQ and -LGNT signals per slot. LBTs that are never a bus master should leave this signal not connected. The motherboard pulls this signal high using a 20K pull-up resistor. When the Bus device asserts this signal, the VL-Bus controller responds by asserting the -LGNT <X> signal forthat slot. The VL-Bus device then has control of the VL-Bus and may hold the bus until the VL-Bus controller removes -LGNT <X>
Memory or 110 Status: This CPU output indicates the type of access cur-rently executing on the VL-Bus. On the motherboard, the -MIlO signal can either be directly connected to the CPU -MIlO signal, or tri-state buffered.
A memory cycle is indicated by -MIlO high, while an 1/0 cycle is indicated by -MIlO low. This signal is driven by the CPU for all CPU-initiated trans-fers. During system 110 bus master or DMA cycles the VL-Bus controller drives this signal according to the values of system 1/0 bus signals -MEMR, -MEMW, -lOR, and -lOW. During Bus master transfers, the VL-Bus device acting as bus master drives this signal.
Table 3.-8. P3 VL-Bus Signal Descriptions (Continued)
Ready Return: This signal establishes a handshake so that the VL·Bus target knows when the cycle has ended. Using this signal is equivalent to the Aeady (-RDY) signal that is tied directly to the CPU or cache controller.
It is always driven by the VL-Bus controller to all VL-Bus masters and tar-gets. For LCLK speeds up to 33 MHz, th is signal is typically asserted in the same LCLK cycle as -LADY is asserted. At higher LCLK speeds it may trail the -LADY signal by one LCLK cycle due to signal resynchronization.
During DMAor system I/O bus master signals, the VL-Bus controller as-serts this signal for one LCLK cycle when the DMA or system I/O bus mas-ter command ends;
System Reset: This active low signal is a master reset that is asserted after system power up and before any valid CPU cycles take place. It is al-ways driver by the system logic or the VL-Bus controller to all VL-Bus mas-ters and targets. It places all devices at a known state before execution begins. Unlike the 386 CPU reset, there is no guaranteed relationship be-tween the rising or falling edges of this signal and the phase of LCLK.
Write Back: This VL-Bus controller output is used to maintain cache co-herency in systems that have a cache structure that requires this
Write Back: This VL-Bus controller output is used to maintain cache co-herency in systems that have a cache structure that requires this