)-NOTE: Assumes jumper E33 . E34
removed.
T1
VALID
NON BUS VECTORED INTERRUPT SEQUENCE
I T3 I Tw I Tw I T4 I T1 I T2 I T3 Tw I T4 I T1
LrL
L: ___ ~~~ __________________
~r-_ --11_ WAIT FOR BUS ACQUISITION
I
r'
----II~
ON·BOARD CIRCUIT READY FROML~
'~
FROM XACKJ ON BUS
I
---i,~~ I _____________
S_lA_V_E_I_D_TO __ Sl_A_V_E_P_IC ____________ . . , }---I--~'~j'~---~'~~ I ____
C_A_SO_._2_0_N_B_US __~--J~
___________________ ....,,_---1'
INTERRUPT TYPE FROM SLAVE PICr---@----
VALIDPI , DATA
NOTE: Assumes jumper E33·E34
installed. - BUS VECTORED INTERRUPT SEQUENCE
Figure 4-7. Multibus access Timing
4-39. BV Interrupt Sequence
The bus vectored interrupt sequence appears to the 8086-2 PU to be similar to the non-bus vectored interrupt sequence with the jumper E33-E34 removed. However, in this case, the interrupt vector comes to the CPU from a slave PIC rather than from the master (on-board) PIC.
Assume for explanation purposes that the master PIC receives an IR6 interrupt request from a slave PIC. The sequence of events that follows is described in the following paragraphs.
A typical bus vectored sequence begins when an interrupt request is sensed on an interrupt line (IR6). Provided that no other higher
priority request is being serviced, the master PIC responds by generating an interrupt request signal (INTR) to the CPU. The CPU responds by
executing an interrupt acknowledge cycle that places status onto its status lines (SO, S1, and S2).
The status lines are decoded by the U85 8288 Bus Controller. The 8288 activates the MCE signal which activates the INTA CYCLE signal and generates a HIGH on ON BD ADR/. The inactive ON BD ADR/ signal enables the 8289 Bus Arbiter, allowing the 8289 to begin arbitration for control of the Multibus interface.
When the 8289 obtains control of the bus, it activates BUS AEN/ which generates a BUS INTA/ signal from the 8288 Bus Controller (U85). The BUS INTA/ signal goes onto the Multibus interface and causes the slave PIC to freeze the internal state of its priority resolution logic. Locally, the BUS INTA/ signal generates the FIRST INTA/ and 8259A INTA/ signals to perform functions as follows.
*
*
The 8259A INTA/ signal allows the master PIC to place the interrupt ID byte onto the CASO through CAS2 lines.
The FIRST INTA/ signal and the T43 signal generate the OFF BD RDY signal to provide a READY input to the CPU, allowing the CPU to complete the first interrupt acknowledge bus cycle.
The second interrupt acknowledge bus cycle activates the MCE signal again, and generates a second INTA/ pluse from th 8288 Bus Controller
(U85) onto the Multibus interface. The functions performed by each are as follows.
*
The MCE signal latches the slave ID byte (on CASO through CAS2) and gates the byte onto the Multibus address lines ADR8/ through ADRA/.*
The INTA/ pulse causes the slave PIC to recognize its slave ID on AD8 through ADA, read the interrupt ID byte, place an interrupt vector onto the Multibus data lines DATO/ through DAT7/, and activate the XACK/ line on the Multibus interface.By activating the XACK/ signal, the slave device indicates that the interrupt vector is available on the Multibus data lines. The XACK/
signal generates another READY signal (OFF BD RDY) to the CPU via PAL device U25, allowing the CPU to read the interrupt vector, terminate the interrupt, and begin servicing the interrupt request.
4-40. FAILSAFE TIMER OPERATION
The iSBC 86/14/30 board contains a Failsafe Timer that generates a bus timeout signal (TIME OUT INTR/) when an expected response from another device (in the form of an XACK/ signal) is too late in arriving to the iSBC 86/14/30 board.
When the jumper E38-E39 is installed and the timeout interval has
elapsed, logic device U1S activates the TIME OUT INTR/ signal to enable generation of the local interrupt signal (LOCAL INTA). The LOCAL INTA signal generates a READY signal to the CPU via the OFF BD RDY signal from PAL device U2S.
The timeout is generated by logic device UlS and components R13 and C7 (lOZBS) and the ALE signal on the iSBC 86/14/30 board. As the board operates, the ALE signal is pulsed for every instruction cycle. If the ALE signal is idle for more than approximately 4 milliseconds, UlS activates the TIME OUT INTR/ signal. Jumper connections on the
iSBC 86/14/30 board allow use of the TIME OUT INTR/ signal (if jumpered properly within the interrupt logic) to interrupt the CPU, indicating that a timeout condition has occurred.
4-41. CHIP SELECT CIRCUIT OPERATION
The iSBC 86/14/30 board contains Programmable Array Logic (PAL) devices that provide address and command decoding to generate the required chip select terms for the opration to be performed. The PAL devices are fused program devices whose output signals are dependent: on the factory
programming performed before shipping the board. The iSBC 86/14/30 board contains 4 PAL devices that provide several functions required for
operation of the board that have been performed on previous types of single board computers via discrete logic components.
The internal operation of the PAL devices, to this point, has been handled as though the device where a black box; when a certain input signal combination occurs, a consistent output results. However, in certain cases, the internal operation of the PAL devices must be known The following paragraphs provide the details of internal operation of each of the 4 PAL devices on the iSBC 86/14/30 board, and includes a formula for each PAL that allows prediction of a resultant signal for a determined input signal combination.
Tables 4-6 through 4-12 describe operation of each PAL, including Boolean equations describing the logic signal flow through the device. The
Boolean equations are listed such that the active level of_the input signals (whether active-high or active-low) and the required state of the input signals (whether the signal must be true or false) can be
determined by the equation. A slash (/) after a signal name indicates that the signal is active-low; a bar over the signal name indicates that the false condition of the signal is required in the operation.
4-42. I/O Chip Select Operation
PAL device U36 decodes the address lines to provide the I/O chip select terms required for the iSBX Bus interfaces, the status register, the 8259A PIC, the 8255A-5 PPI, the 8251A PCI, and the 8253-5 PIT on the iSBC 86/14/30 board. The PAL device is a 20-pin IC that accepts 12 input signals and provides 6 active-LOW output signals.
Two of the inputs are not labeled on the schematic drawing. However, they provide the PAL with an indication as to whether the installed devices on the iSBX Bus interfaces are 8-bit or l6-bit devices. The signals enter the PAL on pins 8 and 9, one signal for each connector.
The functions of each signal on the iSBC 86/14/30 board are listed in Table 4-5. Table 4-6 lists separately each of the 6 output signals from U36 and the conditions required to activate each.
Table 4-5. iSBX~ Bus Width Select PAL INPUT
Pin 9 Pin 8 Interface Operation Selected
Low Low l6-bit operation for both connectors.
High Low 8-bit operation for connector J4, l6-bit operation for connector J3.
Low High l6-bit operation for connector J4, 8-bit operation for connector J3.
High High 8-bit operation for both connectors.
Table 4-6. PAL U36 Operation Output Signal Input Signal Combination
Name
PIO CS/ A7 and A6 and A5 and 10 ADDR
SBX2 CSO/ A7 and A6 and A5 and A4 and
AD
and 10 ADDR and MPRES2/SBX2 CSl/ A7 and A6 and A5 and A4 and
iffiE/
and 10 ADDR and SBX2 8-BIT and MPRES2/or
SBXl CSO/
A7 and A6 and A5 and A4 and AO and I/O ADDR and SBX2 8-BIT and ~MP~RE~S~2/
A7 and A6 and
AS
and A4 andAD
and 10 ADDR and MPRESl/Output Signal Functions
Provides the chip select term for accessing the status register, the 825lA, the 8253-5, the 8259A, and the 8255A-5 devices.
Provides the MCSO/ chip select term for I/O addresses AO through AE (even addresses only) to an 8- or l6-bit iSBX Bus device on J3.
Provides the MCSl/ chip select term for I/O addresses Al through AF (odd addresses only) to a l6-bit iSBX Bus device on J 3.
Provides the MCSl/ chip select term for I/O addresses BO through BF (even addresses only) to an 8-bt iSBX Bus device on J 3.
Provides the MCSO/ chip select term for I/O addresses 80 through 8E (even addresses only) to an 8- or l6-bit iSBX Bus device on J4.
Output Signal Name
SBX1 CS1/
or
I/O ACCESS EN
or
or
Table 4-6. PAL U36 Operation (continued) Input Signal Combination
A7 and A6 and
AS
and A4 andBRE/
and 10 ADDR and SBX1 8-BIT and MPRES1/A7 and A6 and
As
and A4 and AO and I/O ADDR and SBX1 8-BIT and MPRES1/A7 and A6 and AS/
A7 and
A6
and AS and MPRES1/A7 and
A6
and AS and MPRES2/Output Signal Functions
Provides the MCS1/ chip select term for I/O addresses 81 through 8F (odd addresses only) to a 16-bit iSBX Bus device on J 4.
Provides the MCS1/ chip select term for I/O addresses 90 through 9E (even addresses only) to an 8-bit iSBX Bus device on J 4.
Provides the I/O ACCESS signal and I/O bus conditioning for accesses to I/O port address CO through DFH; the on-board LSI devices.
Provides the I/O ACCESS and I/O bus conditioning for access to I/O port address 80
through 9FH, the iSBX Bus I/O address of J4.
Provides the I/O ACCESS and I/O bus conditioning for access to I/O port address AO
through BFH, the iSBX Bus I/O address of J3.
4-43. EPROM Chip Select Operation
PAL device U45 decodes the address lines to provide the PROM chip enable terms required for accessing the on-board EPROM. The PAL device is a 20-pin IC that accepts 11 input signals and provides 3 active-HIGH output signals.
Two of the inputs to the PAL are not labeled on the schematic drawing.
The output signals BANKO and BANK1 are used by U56, a 2-to-4 decoder, to selectively activate the PROM chip enable signals. However, they provide the PAL with an indication as to which of four possible device types are being used; including 2k by 8-bit, 4k by 8-bit, 8k by 8-bit, or 16k by 8-bit devices. The signals enter the PAL on pins 1 and 2 and function on the iSBC 86/14/30 board as listed in Table 4-7. Table 4-8 lists
separately each of the 3 output signals from the PAL device and the conditions required to activate each.
Table 4-7. EPROM Chip Capacity Select PAL INPUT
Pin 1 (SIZO) Pin 2 (SIZ1) Chip Size Selected
Low Low 16k by 8-bit capacity; 27128 chips.
Low High 8k by 8-bit capacity; 2764 chips.
High Low 4k by 8-bit capacity; 2732 chips.
High High 2k by 8-bit capacity; 2716 chips.
Table 4-S. PAL U45 Operation Output Signal Input Signal Combination
Name
Output Signal Functions
Decodes the address as being
Table 4-8. PAL U45 Operation (continued)
Output Signal Input Signal Combination Output Signal Functions Name
or MEM and A13 and A12 and All and A10 and AF and
SIZO and SIZl Decodes the address as being within the PROM address space
FOOOO through F7FFF.
BANK 1 (pin 15) MEM and A13 and A12 and All and A10 and AF and AE and AD and AC and
SIZO and SIZl Decodes the address as being within the PROM address space FEOOO through FEFFF.
or MEM and A13 and A12 and All and A10 and AF and AE
and AD and SIZO and SIZl Decodes the address as being within the PROM address space FCOOO through FDFFF.
or MEM and A13 and A12 and All and A10 and AF and AE
and SIZO and SIZl Decodes the address as being within the PROM address space F8000 through FBFFF.
or MEM and A13 and A12 and All and A10 and AF and
SIZO and SIZl Decodes the address as being within the PROM address space FOOOO through F7FFF.
4-44. RAM Chip Select Operation
PAL device U46 decodes the address and status lines to provide the access control signals required for accessing the dual port RAM. The PAL device is a 20-pin IC that accepts 11 input signals and provides 4 active-HIGH output signals.
Two of the inputs to the PAL (SIZO on pin-2 and SIZl on pin-3) are not labeled on the schematic drawing. However, they provide the PAL with an indication as to which of four possible capacities of the RAM array are present on the board. The functions performed by the signals are listed
in Table 4-9. Table 4-10 lists separately each of the 4 output signals from the PAL device and the conditions required to activate each.
Table 4-9. RAM Array Capacity Select PAL INPUT
Pin 2 (SlZO) Pin 3 (SIZ1) Array Capacity Selected
Low Low 256k byte capacity.
Low High l28k byte capacity.
High Low 64k byte capacity.
High High 32k byte capacity.
Table 4-10. PAL U46 Operation Output Signal Input Signal Combination
Name
MEM CMD CMD Q2 and MEM and LSl
or CMD Q2 and MEM and LSO
LOCAL DP WT/ CMD Q2 and MEM and LSl and LSO
LOCAL DP RD/ CMD Q2 and MEM and LSl
RAM ACCESS MEM and A13 and A12 and All and A10 and AF and SIZO and SIZl
Output Signal Functions
Decodes the command from the CPU or the 8288 Bus Controller as being a memory READ command.
Decodes the command from the CPU or the 8288 Bus Controller as being a memory WRITE
command.
Decodes the command as being one to WRITE to dual port RAM.
Decodes the command as being one to READ from dual port RAM.
Decodes the address as being within the dual port RAM memory address space (local addresses 00000 through 07FFF, or 32k); iSBC 86/14 board only.
Table 4-10. PAL U46 Operation (continued)
Output Signal Input Signal Combination Output Signal Functions Name
or MEM and A13 and A12 and All and Ala and
SI20 and SI21 Decodes the address as being within the dual port RAM memory address space (local addresses 00000 through OFFFF, or 64k);
iSBC 86/14 board with iSBC 300A board only.
or MEM and A13 and A12 and
AIT and SI20 and SI21 Decodes the address as being within the dual port RAM memory address space (local addresses 00000 through 1FFFF, or 128k);
iSBC 86/30 board only.
or MEM and A13 and A12 and
SI20 and SI21 Decodes the address as being within the dual port RAM memory address space (local addresses 00000 through 3FFFF, or 256k);
iSBC 86/30 board with iSBC 304 board only.
4-45. Bus Control Operation
PAL device U25 provides control over the Mu1tibus and local bus activity on the iSBC 86/14/30 board. The PAL device is a 20-pin IC that accepts 13 input signals and provides 4 output signals. Table 4-11 lists the 4
output signals and the conditions required on the inputs to activate each.
Table 4-11. PAL U25 Operation
Output Signal Input Signal Combination Output Signal Functions
~~
LOCAL INTA
or
DT/R BUS
or
OFF BD RDY
or
or
or
WORD XMIT
or
BUS AEN/ and BUS INTA/ Provides the INTA input to the master PIC for a BV or NBV interrupt cycle (with jumper E33-E34 installed).
ON BD ADR/ and INTA/ Provides the INTA input to the master PIC for a NBV interrupt cycle.
BUS AEN/ and BUS RD CMD/ Conditions the data bus buffers to the Multibus to the output direction for the data transfer.
BUS AEN/ and ON BD DTR Conditions the data bus buffers to the Multibus to the input direction for the data transfer.
FIRST INTA/ and T43
59 DEN and T43
XACK and BUS AEN/
TIME OUT INTR/
ABO
INTA CYCLE and 59 DEN and BUS AEN/
Provides the CPU with READY after the first INTA cycle of either a BV or a NBV interrupt.
Provides the CPU with READY after the second INTA cycle of a NBV interrupt operation.
Provides the CPU with READY after the second INTA cycle of a BV interrupt operation.
Provides the CPU with READY if a failsafe timeout occurs.
Enables the data bus buffers to perform a word operation when address is even.
Enables the data bus buffers to perform a byte operation if the 3 signal conditions are present during a BV interrupt cycle.