10:05 THE INSTRUCTION PROCESSING FUNCTION GENERAL DESCRIPTION
The instruction processing function contains all the elements
necessary to decode and execute the instructions in the instruction set for the 4331 Processor. I/O instructions are partially processed by the instruction processing function and partially processed by the
appropriate channel or I/O adapter.
All instruction execution functions and most channel operations are microcode controlled,. Microinstructions are four bytes in length.
Control storage for the residence of instruction processing function microcode is 64K or 128K bytes. The data path within the instruction processing function is four bytes wide. Extensive parity checking is done within the instruction processing function to ensure data validity.
certain basic control and service functions are provided for the 4331 Processor by the support processor subsystem, instead of by the
instruction processing function,. The support processor subsystem is controlled by a microcoded controller (support processor 1) that
contains its own control storage (see discussions in sections 10:15 and 50:15).
The instruction processing function in the 4331 Processor has a variable-length cycle time. Cycle time varies from 200 nanoseconds to 1600 nanoseconds in 100-nanosecond increments, depending on the
instruction..
Elements included in the instruction processing function to perform instruction execution are a four-byte-wide arithmetic logic unit, a four-byte-wide shifter, fullword working registers, and semiautomatic hardware facilities designed to speed up instruction execution.. An instruction buffer and control storage buffer are also present,.
Instructions are fetched from processor storage and placed in a 16-byte instruction buffer from which they are fetched for execution,. The use of such a buffer avoids most delays that could be caused by the refreshing of processor storage. Instruction buffer loading requires 2. 4 microseconds,.
Instructions are fetched for execution from the 16-byte instruction buffer at a rate of 200 nanoseconds per halfword,. Instructions are fetched from the buffer as long as the next required instruction is contained in the buffer,. If the required instruction is not currently in the buffer or only partially contained in the buffer, the entire buffer is reloaded, beginning with the required instruction.
The instruction buffer is also reloaded for each successful branch, whether or not the instruction required is present in the instruction buffer. This is done to properly handle self-modifying code. There is no overlap of instruction buffer filling and instruction execution (that is, no instruction pref etching) ,_
The microcode that controls instruction processing function operations is partially resident in reloadable control storage and
partially resident in processor storage (see discussion of processor and control storage in Section 10:10). To avoid most delays caused by the
refreshing of control storage (and processor storage), a 64-byte control storage buffer is present in the instruction processing function,. This buffer can· contain 16 four-byte microinstructions at a time.
Any microinstruction in the control storage buffer can be accessed directly,. The fetching of one microinstruction and its placement in an operation register for execution requires 100 nanoseconds. When the next required microinstruction is not present in the control storage buffer, the buffer is refilled with the 64-byte block of
microinstructions that· contains the needed microinstruction. The 16 microinstructions are fetched from control storage or processor storage, as required.
A buffer fill from control storage requires 300 nanoseconds while 2.6 microseconds are required to fill the control storage buffer from
processor storage,. Instruction execution waits until the control storage buffer is refilled.
The instruction processing function accesses a 2K-byte data local storage area as required during the execution of instructions. This data local storage conta~ns the control registers, general registers, floating point registers, all the ~ubchannels used by the byte
multiplexer channel and Communications Adapter, all unit control words (UCWs) used by the channels and I/O adapters, work registers, and
various work areas. The work areas are used by certain I/O adapters and emulator routines .•
The address translation facilities provided for System/370 and
ECPS:VSE modes are discussed in Section 15. The ECPS:VM/370 feature is discussed in Section 18, which describes a virtual machine environment.
other significant new features of the instruction processing function of the 4331 Processor for Model 30 and 40 users are discussed in the
remainder of this subsection.. A complete discussion of hardware and I/O differences between the 4331 Processor and the Model 20 is contained in Section 60.
CONTROL REGISTERS
The program states in which the 4331 Processor is operating are reflected in the current program status word (PSW) and in processor status indicators called control registers, which are contained in data local storage in the 4331 Processor.. Up to 16 control registers, 0-15, can be addressed,. Certain control registers are used only when EC mode is in effect. Control registers are program-addressable only when the processor is in the supervisor state.
A control register can be set with the LOAD CONTROL instruction, and its contents can be placed in processor storage with the STORE CONTROL instruction.. Additional status indicators contained in control
registers are required in order to support new functions. A control register is 32 bits in size.
Note that control reg.ister assignments for functions that are implemented in both 4300 Processors and System/310 processors are the same. Control register bits that control functions not supported in 4300 Processors (multiprocessing, extended machine check logouts, etc.) are unassigned in 4300 Processors for compatibility purposes.
BASIC CONTROL MODE
As indicated previously, the contents, layout, and function of fixed locations 0-127 in 4300 PJ'ocessors and System/310 processors that are operating in BC mode are identical to these locations in most System/360
processors'with the exception of bit 12 in the PSW, which specifies EBCDIC or ASCII mode in System/360 processors and BC or EC mode in 4300 Processors and System/370 processors. ASCII mode is not implemented in 4300 Processor or System/370 architecture, nor was the mode bit
supported by IBM programming systems provided for Systeml360 processors, because System/360 USASCII-8 did not become the ASCII standard.
However, ASCII-encoded tapes are supported by certain DOS/VS,
DOS/VSE, and OS/VS language translators and service programs. That is, ASCII-mode tapes are accepted by certain DOS/vS, DOS/VSE, and OS/VS language translators and service programs as input and converted to EBCDIC for processing. The capability of writing ASCII-mode tapes is also provided .•
TO improve system availability and serviceability, implementation of the machine check class of interruption for the 4331 Processor i~
considerably altered from its implementation in Models 30 and 40 (see Section 50). However, the other four interruption classes (I/O, SVC, program, and external) operate in the same manner on Models 30 and 40, and the 4331 Processor except for the (1) expansion of external
interruption masking, (2) expansion of channel masking, and (3) addition of program and external interruptions to support new features in the 4331 Processor. Imprecise interruptions do not occur in the 4331
Processor,. '
Five external subclass mask bits, which allow selective masking of external signals (2-7), interval timer, CPU timer, clock comparator, and operator console interruptions, are provided in control register
o.
When the PSW ex,ternal mask bit is off, the processor is disabled for all external interruption types,. When the PSW external mask bit is on, an external interruption occurs for an external interruption type only if its associated subclass mask bit is on also,.
Execution of the SET SYSTEM MASK (SSM) instruction is under the control of the SSM mask bit in control register O. When the SSM mask bit is on, an attempt to execute an SSM instruction causes a program interruption without execution of the SSM instruction. When the SSM mask bit is off, SSM instructions are executed as usual.
This SSM interruption is implemented to enable existing programs that were written for System/360 processors or for System/370 BC mode of operation to execute correctly in EC mode without modification of the system mask field addressed by existing SSM instructions. When an SSM interruption occurs, the contents of the BC mode format system mask indicated by the SSM instruction can be inspected and the appropriate EC mode mask bits can then be set by an SSM simulation routine.
EXTENDED CONTROL MODE
Extended control mode is a major facility that is not implemented in Systerr/360 architecture. Facilities that depend on ,which mode is in effect are discussed below and apply to System/370 and ECPS:VSE modes unless otherwise noted. Any item not covered operates identically in BC and EC modes,.
When a 4331 Processor operates in System/370 and EC modes, it operates exactly like a System/370 processor operating in EC mode, except for the basic architecture implementation differences previously listed in Section 05:10.
Change. in PSW Format
When a 4331 Processor operates in Ee mode, the format of the PSW differs from its Be mode format,. Both PSW formats are shown in Figure
10 .• 05 .• 1,. In Be mode, the PSW does not contain individual channel mask bits, an instruction length code, or the interruption code for a
supervisor call, external, or program interruption.. The channel masks are contained in control register 2, and the other fields are allocated permanently aSSigned locations in the fixed lower processor storage area above address 127.
*5 Translation mode (OAT feature mask) 6 I/O summary mask address translation for System/310 mode and program event recording) and for the addition of summary mask bits (such as channel and I/O masks).
Use of a single mask bit to control the operation of an entire facility (such as program event recording) or an entire interruption class (such
as I/O and external) simplifies the coding required to enable and disable the processor for these interruptions,.
Note that the Be and Ee mode PSW formats shown in Figure 10.05.1 are the same for System/370 and ECPS:VSB modes with one exception. Bit 5, which enables and disables the dynamic address translation facility for System/310 mode, must be zero for ECPS:VSE mode.
Change in Permanently Assigned Processor Storage Locations
When a 4331 Processor operates in EC mode, the number of permanently assigned locations in lower processor storage is increased to include fields for storing instruction length codes, interruption codes (for supervisor call, external, and program interruptions), program event recording data, the I/O address for an I/O interruption, and an exception address for the address translation capability.
The fixed storage layout for BC mode is shown in Figure 10.05.~ and for EC mode in Figure 10 .• 05,.3. The format of locations 0 to 511 is the same for 4300 Processors and System/310 processors for fields
implemented in both. System/310 processors implement additional processor-dependent fields, such as a region code in locations 252 to
255, that are reserved fields in 4300 Processors,. The access exception field shown in Figure 10,.05.2 is not implemented in System/310
processors for Be mode operations. Locations 0 to 127 are the same for 4300 Processors and System/360 processors.
Channel Masking Changes
When a 4331 Processor operates in BC mode, interruptions from each channel are controlled by the summary I/O mask bit (bit 6) in the current PSW and an individual channel mask bit in control register 2.
In the 4331 Processor, bits 0 to 3 in control register 2 are assigned to control channels 0 to 3, respectively. Both the summary mask bit and the appropriate individual channel mask bit must be on in order for an interruption from a given channel to occur. In BC mode, interruptions from channels 0 to 3 are controlled only by the channel mask bits (bits
o
to 3) in the currentpsw.
Expansion of Storage Key Size
The size of the storage key associated with each 2K storage block for store and fetch protection is seven bits (as in System/310) instead of five bits, as in System/360. The two additional bits (reference and change) are included for use with address translation and are discussed in Section 15:10. The SET STORAGE KEY instruction sets a seven-bit key regardless of the mode, BC or EC, in effect. The INSERT STORAGE KEY instruction causes a five-bit or a seven-bit key to be loaded into a register, depending on whether BC or EC mode, respectively, is in effect.
BC MODE FIXED AREA 0-159
't Floating point register save area
r
384 £ 1 - - - 1
l' General register save area 'r
4 4 8 . . c t - - - f ; t
l ' Control register save area l'
Figure 10 .• 05 .• 2 .• BC mode fixed processor storage locations 0 to 511 Revised definitions of these instructions to include BC/EC mode differences are contained in the System/370 and 4300 Processor
Principles of Operation publications. programs that operate in BC mode and that use LOAD PSW and/or SET SYSTEM MASK (SSM) instructions must be
facilities that are mode-dependent. System/370 programs that operate in
Limited channel logout 180 Reserved Reserved
J
0I
I/O address 188 Reserved ,L Floating point register save area~ 384 ,.L '"r General register save area
r
«8
I
~ Control register save area r~ ..!Figure 10. 05,.3. EC mode fixed processor storage locations 0 to 511 Changes to Certain Instruction Definitions
As a result of the differences between the PSW format and the
permanently assigned processor storage locations in EC and BC modes, the definition of certain instructions is affected.
Instructions provided for System/360, System/370, and 4300 Processors whose definition is altered for EC mode are:
BRANCH AND LINK (RR, RX) INSERT STORAGE KEY
LOAD PSW
SET PROGRAM MASK
SET STORAGE KEY SET SYSTEM MASK SUPERVISOR CALL
Program Event Recording
program event recording (PER), a standard feature for the 4331 Processor, is designed to assist in program debugging by enabling a program to be alerted to any combination of the following events via a program interruption:
• Successful execution of any type of branch instruction
• Alteration of the contents of the general registers deSignated by the user
• Fetching of an instruction from a processor storage area defined by the user
• Alteration of the contents of a processor storage area defined by the user
The PER feature can operate only when EC mode is in effect and the PER mask, bit 1 of the current PSW, is a one. Control register 9 (bits
o
to 3) is used to specify which of the four PER event types are to be monitored. A PER program interruption is taken after the occurrence of an event only if both the PER mask bit and the respective event mask bit in control register 9 are on. Control register 9 (bits 16 to 31) also specifies which of the 16 general registers are to be monitored if monitoring of this event is specified,. Control registers 10 and 11 indicate the beginning address and the ending address, respectively, of the contiguous processor storage area that is to be monitored forinstruction fetching and/or alteration..
When an event that is being monitored is detected, PER hardware causes a program interruption, if the PER mask bit is on, and the identification of the type of event is stored in the fixed processor storage area (location 150). The address of the instruction associated with the event is also stored (locations 153 to 155). program event interruptions are lost if they occur when the PER mask bit or the particular event mask bit is off. In the 4331 Processor, additional processor time is required to execute instructions when program event recording is operative.
When System/370 mode is in effect, if dynamic address translation mode is specified when PER is active, virtual storage addresses instead of real storage addresses (discussed in Section 15) are placed in the control registers to monitor references to a contiguous virtual storage area. For ECPS:VSE mode, virtual storage addresses are always used.
EXPANDED INSTRUCTION SET
The instruction set for the 4331 Processor is a superset of that provided fer System/360 processors. It consists of the System/360 instruction set plus several new instructions that support System/310 and 4300 Processor architecture and provide additional functions. The
standard instruction set contains all the 4331 Processor instructions (no instructions are optional).
The standard instruction set for the 4331 Processor consists of (1) all System/370 instructions except those associated with features not implemented in 4300 Processors (READ DIRECT, WRITE DIRECT, and the four multiprocessing instructions), (2) several control instructions that are valid only for ECPS:VSE mode, and (3) the MOVE INVERSE instruction. The ECPS:VSE mode instructions, discussed in section 15:15, are the only 4300 Processor instructions that are not also available for System/370 processors.
The STORE CPU ID instruction permits a program to determine the processor and version of the processor upon which it is operating and provides the processor serial number.
The STORE CHANNEL ID channels present in the multiplexer),. Selector when it is operating in instruction is issued.
instruction can be used to identify the types of system (selector, byte multiplexer, and block is indicated for the block multiplexer channel selector mode at the time the STORE CHANNEL ID Some of the other new instructions are:
• General purpose instructions
Several general purpose instructions, which can be of benefit to both control and processing program performance, are provided.
SHIFT AND ROUND DECIMAL provides right or left shifting of packed decimal data using a single instruction. This instruction can save from 6 to 18 byte$ of instruction storage and instruction execution time for each decimal shift and round operation performed in
commercial processing.
MOVE LONG provides for the movement of up to 16 million bytes from one location in processor storage to another with a single
instruction, thereby removing the System/360 limitation of 256 bytes per move,. A check for the possibility of destructive overlap is made by the hardware prior to the movement of any data and the MOVE LONG instruction is not executed if operand destruction can occur.
This instruction can eliminate the necessity of multiple move instructions or the inclusion of move subroutines. The format and operation of MOVE LONG facilitates efficient record blocking and deblocking, field padding, and storage clearing, which are
operations frequently performed in commercial processing.
The COMPARE LOGICAL LONG instruction can be used to compare logically two fields of up to 16 million bytes in length, thus removing the System/360 256-byte limit on byte compares. In addition, when an unequal compare occurs, the two characters that caused the inequality are identified.
The MOVE LONG and COMPARE LOGICAL LONG instructions are
interruptible. Thus, when an I/O operation terminates during their execution, the interruption is taken and the channel is not held up awaiting termination of what might be a lengthy move or compare.
COMPARE LOGICAL, -INSERT, and STORE CHARACTERS UNDER MASK instructions provide byte addressability within the general registers and permit nonword-size data that is not on a word boundary to be compared with data in a register, loaded into a register, and stored from a register. These three instructions can be of most benefit to control program programmers, to compiler writers, and to others who must manipulate processor storage addresses,.
The MOVE INVERSE instruction is standard in the 4331 Processor. It causes bytes from the second operand to be fetched in right-to-left sequence and placed in left-to-right sequence in the first operand location. The instruction is useful for handling languages in which writing occurs right to left.
• Control instructions
STORE THEN AND SYSTEM MASK and STORE THEN OR SYSTEM MASK are two privileged instructions that affect the system mask (bits 0 to 7 in the current PSW),. The STORE THEN AND SYSTEM MASK instruction
provides, via a single instruction, the capability of storing the current system mask for later restoration, while selectively zeroing certain system mask bits,. The STORE THEN OR SYSTEM MASK provides system mask storing and selective setting of system mask bits to ones. These two instructions simplify the coding required to alter the system mask, particularly when the existing settings must be
provides, via a single instruction, the capability of storing the current system mask for later restoration, while selectively zeroing certain system mask bits,. The STORE THEN OR SYSTEM MASK provides system mask storing and selective setting of system mask bits to ones. These two instructions simplify the coding required to alter the system mask, particularly when the existing settings must be