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TELETYPE TRANSMITTER

Im Dokument LOGIC HANDBOOK (Seite 187-193)

circuit parallel·to.serial teletype code converter, self contained on a double·height module. This unit in·

cludes all of the parallel to serial conversion, buffering, gating, and timing necessary to transfer information in an asyncronous manner between a parallel binary device and a serial teletype line. Either a 5·bit or 8·bit parallel character can be assembled into a 7.0, 7.5, or 8.0 unit serial character or a 10.0, 10.5, or 11.0 unit serial character, respectively, by the W707 through the use of selective jumpers on the module.

When the conversion is complete, the necessary one unit negative voltage start signal and a ground level stop signal of 1.0, 1.5, or 2.0 units have been added to the original parallel character and transmitted over the serial line. The serial character is transmitted with the start signal first, followed by bits 1 through 8 in that order, and completed by the stop signal.

One·half unit after the stop signal is put on the serial line, the flag is set indicating that the previous.

character has been transmitted and that a new paral·

lei character can now be loaded into the W707.

To obtain additional Tel.etype applications data write for Applications Note AP-W·1. loads the parallel character into the W707. Typically this pulse is generated after a Flag Output has been

ot t: .

t transmission. Ground levels on bit inputs represent a logical 1 or a Teletype "mark," and generate a ground output on the serial line at the corresponding bit times.

vides a ground level Strobed Flag Output signal when the flag is set.

POWER CLEAR: Same input signals and loading as for Flag Strobe. Initialization of module elements by a Power Clear signal is not necessary if the first

&erial character transmitted.after power turn·on need

not be correct. When not used, Power Clear can be left disconnected.

WAIT: This input is available for use with the W708 in half duplex operation. Internal logic levels of +3.6 and ground appear at this input. It must not be output during character transmission. A logical 1 output is a ground level. If inductive loads are driven by this output, diode protection must be provided

INVERTER: Pins BJ and AP are the input respectively of an inverter that can be used for any needed buffer·

ing. Input load is 1.8 ma at -3 volts.

JUMPERS: Jumper positions are indicated on the top view physical sketch shown in Figure 3. The W707 is shipped with all jumpers in position.

PARALLEL INFORMATION

COMPUTER NUMBER I

~

-,---,

POWER: -15(8}/3 ma; +3.6 volts/400 mao This power is available from a W705 or any commercial supply that has an output regulation of ±5%.

COMPUTER NUMBER 2

Figure 2. Computer·to·Computer Serial Transmission.

2.0uni!s

.1..

()o----o()

D D

Q :1.0

Db~D 0 0

: units ~

0

..-vvv-e

D

6 Q 6 'La :units

D 0

..-vvv-e ..-vvv-e ~ ~ ~

0 D

~ ~ ~

D D D

~ ~ ~ ...-vvv-e ..-vvv-e ~ ~

D

~ ~

D 9?

9

:5

I bit

D D

...-vvv-e ..-vvv-e ..-vvv-e ...-vvv-e ..-vvv-e ...-vvv-e

o-jf-o

andl 1.0, 1.bit 8 .-vvv-e

D

D""li~l i, D D D

~ ~ ~ ~ ~ ~ ~ ~ ~

~

Figure 3. W707 Jumper Diagram.

TYPE W708

8 X CLOCK

TO W706 CLOCK INPUT TELETYPE SERIAL INPUT

TO W707 CLOCK INPUT CLOCK ENABLE FROM W706

TELETYPE TO POWER CLEAR W706

POWER CLEAR INTERFACER TO CLEAR FLAG W706

CLEAR FLAG 1

CLEAR FLAG 2 TO WAIT W707

W70B TELETYPE INTERFACER

The W708 provides special gating controls and clock synchronization for Teletype and data communica-tions systems, when used with the W706 and W707 Teletype modules. For additional applications data and more complete specifications on the W708, write for Applications Note AP-W·l.

ADDITIONAL FUNCTIONAL CAPABILITY SPIKE ELIMINATOR: This gating structure provides one·half unit start pulse· noise rejection so that long noisy teletype lines can interface with the W706.

WAIT: Provides the necessary control gating so that the W706 and W707 can be used in half·duplex operation. This control section is used to hold W707 transmission while the W706 is receiving a character.

CLEAR FLAG CONVERTER: This control provides ad·

ditional gating so that the W706 flag can be cleared in either of two modes during half·duplex operation.

SINGLE CLOCK CONVERTER: Reduces the number of clocks needed in a W706 and W707 Teletype sys·

tem from two to one. This control also allows the use of a non·gateable clock such as the R405 with such a system. The frequency of the required clock is eight times the serial transmission frequency. All start·stop synchronization of the W706 clock input is provided.

POWER: -15(8)/25 ma; +3.6 volts/200 mao This power is available from a W705 or any commercial supply that has an output regulation of ±5%.

RELAY

cir-cuit. When the protecting circuit feature is desired, Nand P (T, U) should be connected together, and the external circuit Connected to P and R (U, V).

To use the relay without the pr.otecting circuit, the external circuit should be connected between M and R (S, V). The protecting circuit consists of a capaci-tor and a parallel combination of an induccapaci-tor and a resistor. The protection circuit slows down current and voltage rise time at the time of contact closure

INPUT: A Standard Level of -3v operates the relay.

Input load is 1 rna at ground, 0 rna at -3v, shared by inputs at ground. Pins F and "K are for use only with diodes such as R001 and R002. A maximum of 6 in. of wire may be attached to these points.

OUTPUT: The relay contacts close when the input requirements are met. Maximum contact ratings are 250v, 500 rna, 10 watts maximum.

I>OWER: -15v/124 rna; + 1 Ov(A)f 0.6 rna.

TYPE W802

(double height module)

W802 RELAY MULTIPLEXER

The W802 Relay Multiplexer contains eight double-pole, normally open reed relays. One of its uses is to address memory lines in memory testers. It can also be used as a low-speed multiplex switch where the grounded, low-noise performance of the A111 multiplexer is not required. Maximum closing time:

1.5 msec; typical opening time: 500 "sec.

INPUTS: Each driver is a 1 rna load shared among

its grounded inputs. Contacts close when inputs are negative.

OUTPUTS: Relay contacts rated at 250v, 500ma, 10 walts maximum. Contact resistance typically 250 milliohms.

POWER: +lOv(A)/2 rna; -15v(B)/20 rna plus 25 rna per energized relay (220 rna max for all relays energiied).

Type

These 10 blank modules offer convenient means of integrating special circuits and even small mechanical components into a FLIP CHIP system, without loss of modularity. Both single· and double·size boards are supplied with contact area etched and gold plated. The W990 Series modules provide connector pins on only one module side for use with H800 connector blocks. W970 series modufes have etched contacts on both sides of the module for use with double

density connectors Type H803. .

Pins Description Handle

18 Bare board, split-lug terminals attached

36 Bare board, split-lug terminals attach~

18 Copper clad, to be etched by user separate 36 Copper clad, to be etched by user separate 18 Perforated, 0.067" holes, 18 with attached

etched lands. The holes are on 0.2"

c~nters. both horizontally and vertically.

36 Perforated, 0.067" holes, 36 with attached etched lands. The holes are on 0.2"

centers, both horizontally and vertically.

36 Bare board, no split lugs, similar attached

Im Dokument LOGIC HANDBOOK (Seite 187-193)

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