SysCore Boards

The three generations of SysCore boards realized so far are presented in this section. All three boards implement theSysCore Architecture.

D.2.1. SysCore Board Version 1

Figure D.3.:TheSysCore Board Version 1 TheSysCore Board Version 1, as pictured in

figure D.3, is the pre-prototype of the CBM Read-Out Controller (ROC). It is based on an Xilinx Virtex-4 FX20 FPGA and its development was the first step towards a common read-out controller board for CBM. It was used to develop a very first read-out chain for the nXYTER chip, the nXYTER Kludge Kit¹. First research projects regarding radiation mitigation, an implementation of a fault tolerant

Soft-Core CPU, were also carried out on this platform [Eng09, page 61/62]. Being a pre-prototype and the first implementation of its kind, the board naturally had some teething problems. Therefore, only five boards were produced and it was quickly superseded by theSysCore Board Version 2.

TheSysCore Board Version 1item list²:

• Xilinx Virtex-4 XC4VFX20, in Speedgrade -11 for boards with PCIe, and in Speed-grade -10 for boards without PCIe

• Actel ProASIC3 Flash FPGA (type A3P125_FGG144) as on-board configuration con-troller for power-on configuration for the Xilinx FPGA and also acting as radiation mitigation engine

• Two 64 Mbit Flash memories (type Macronix MX29LV640B) to store the configura-tion bits for the Xilinx FPGA

• FTDI FT2232C to externally configure the Xilinx FPGA and to communicate with a PC (USB 1.1)

• Two 128 MByte DDR1 SDRAM with 16 bit interface to Xilinx FPGA

• 2.5 Gb optical link, via Virtex-4 MGTs and any SFP compatible transceiver

• 10/100 MBit Ethernet (Virtex-4 on-chip MAC, Intel LXT971ALC PHY, and HALO HFJ11-2450E-L12 MAG)

1see https://cbm-wiki.gsi.de/foswiki/bin/view/DAQ/N-XYTER-KludgeKit

2for detailed technical specification, see https://cbm-wiki.gsi.de/foswiki/bin/view/DAQ/SysCoreV1

• two 80 pin connectors, each with 31 LVDS capable pairs as main user IO interface

• 1-lane PCIexpress, only on two boards

• SD card connector, RS232, JTAG, ...

D.2.2. SysCore Boards Version 2.X

Figure D.4.:TheSysCore Board Version 2.2

The SysCore Board Version 2.0 is the sec-ond iteration of the CBM Read-Out Con-troller prototype, based very closely on the hardware and layout of it’s predecessor, theSysCore Board Version 1. The problems that could be identified with the SysCore Board Version 1 were fixed, some minor design optimizations were implemented (e.g. different form factor for the user IO connectors), and the focus was narrowed on those features that were really signifi-cant for CBM use cases at the time, i.e. support of PCIe was dropped.

In 2008, the board was used the first time as part of thenXYTER Starter Kit³. It soon became a well established resource in CBM detector test experiments, especially when nXYTER or GET4 chips were involved. One board could interface up to four nXYTER and up to 16 GET4 chips, either be read out via Ethernet or via CBMNet (see chapter 4.1).

Soon the demand exceeded the number of available boards. To overcome this short-coming, a new series of boards was ordered. Thereby, the opportunity was used to uti-lize the new boards with a bigger FPGA and a pinout that is better optimized for the nXYTER front-end boards. First, two boards were fabricated to test the changes in the layout (SysCore Board Version 2.1). They were utilized with XC4VFX60 FPGAs that hap-pened to be available in the collaboration at the time as left over of a different project.

Then the the major series with XC4VFX40 FPGAs were produced (SysCore Board Version 2.2) [DRC⁺13].

TheSysCore Board Version 2.Xitem list reads as follows⁴:

• Xilinx Virtex-4, XC4VFX20 (Version 2.0), XC4VFX60 (Version 2.1), XC4VFX40 (Ver-sion 2.2), all in Speedgrade -10

• Actel ProASIC3 Flash FPGA (type A3P125_FGG144) as on-board configuration con-troller for power-on configuration for the Xilinx FPGA and also acting as radiation mitigation engine

• Two 64 Mbit Flash memories (type Macronix MX29LV640B) to store the configura-tion bits for the Xilinx FPGA

3see https://cbm-wiki.gsi.de/foswiki/bin/view/NXYTER/NXYTER-StarterKit

4for more details, see https://cbm-wiki.gsi.de/foswiki/bin/view/NXYTER/SysCoreV2

• FTDI FT2232C to externally configure the Xilinx FPGA and to communicate with a PC (USB 1.1)

• Two 128 MByte DDR1 SDRAM with 16 bit interface to Xilinx FPGA

• 2.5 Gb optical link, via Virtex-4 MGTs and any SFP compatible transceiver

• 10/100 MBit Ethernet (Virtex-4 on-chip MAC, Intel LXT971ALC PHY, and HALO HFJ11-2450E-L12 MAG)

• Two 80 pin connectors, each with 32 LVDS capable pairs, as main user IO interface

• SD card connector, RS232, JTAG, ...

Most of firmware development and all in-beam tests described in this thesis are carried out using these version 2.X boards.

D.2.3. SysCore Board Version 3

Figure D.5.:TheSysCore Board Version 3 TheSysCore Board Version 3is a new

imple-mentation of the SysCore Architecturethat became available in 2013. Only some parts of the layout of the SysCore Board Version 2, e.g. the Actel ProASIC based configu-ration controller, were reused. The moti-vation for this re-implementation is cost.

With the Series 6 FPGAs, Xilinx started to equip also their low budget Spartan-FPGAs with all required features for im-plementing the SysCore Architecture,

espe-cially Dynamic Partial Reconfiguration for scrubbing and high speed interfaces for fast data transport [AGM11].

The flexibility of theSysCore Board Version 3allows for its usage as prototyping plat-form in a number of subsystems. Of course, the use cases of theSysCore Board Version 2, the read-out of the nXYTER and the GET4 chips, remain. Additional use cases are the read-out of FEElink interface based ASICs, CBMNet HUB chip development, and DPB development [GGMK13].

With a big Spartan FPGA, about five times more fabric resources are available com-pared to the Virtex-4 FX-40, however, those resources are slower. High clock frequencies of up to 250 MHz as used in the Virtex-4 are not realistic for Spartan-6 designs. There-fore, the existing 250 MHz logic was adapted to 125 MHz clock frequency. On the other hand, the bigger size of the Spartan-6 allowed to fully utilize the higher connectivity of theSysCore Board Version 3. For example, theSysCore Board Version 3based firmware for the GET4 read-out can interface up to 57 GET4 chips, while theSysCore Board Version 2 firmware only supported 16 GET4 chips.

TheSysCore Board Version 3item list⁵:

• Xilinx Spartan 6 LX150T in Speedgrade -3

• Actel ProASIC3 Flash FPGA (type A3P600_FGG144) as on-board configuration con-troller for power-on configuration for the Xilinx FPGA and also acting as radiation mitigation engine

• 512 MB Flash memory (type Micro MT29F4G16ABADAWP) to store the configura-tion bits of the Xilinx FPGA

• Cypress CY7C68013A-56 to externally configure the Xilinx FPGA and to communi-cate with a PC (USB 2.0)

• 128 MB DDR3 SDRAM (type MT41J64M16B-187E) with 16 bit interface to Xilinx FPGA

• 3x 2.5 Gb optical link, via Virtex-4 MGTs and any SFP compatible transceiver

• National LMK03200 jitter cleaner

• two FMC-HPC connectors as main user IO interface

• SD card connector, PMOD connectors, JTAG, ...