Chapter VII Data Communications
7.1 SYNCHRONOUS COMMUNICATIONS CONTROLLER 4015 WITH CLOCK OPTION 4020 AND PARITY OPTION 4021
This controller provides complete bidirectional interfacing between a Data General computer and a Bell 201, Bell 301 or equivalent synchronous data set. Although mounted on a single circuit board, the con-troller is actually two independent interfaces, allowing simultaneous reception and transmission of data. Each interface is connected separately to the data channel, so the program need only set up an interface for receiving or sending and all transfers to and from memory are then handled automatically. To operate with the data channel, each interface has an address counter and a word counter as well as a data shift register for handling serial character transfers. The controller also contains equipment for automatic answering of incoming calls.
Device codes for the receiver and transmitter are 40 and 41 respectively. Additional controllers connected use device code, pairs 42-43, 44-45, . . . , 74-75, where in each case the receiver uses the even code, the transmitter the odd code.
The controller is available in a number of configurations. Characters may contain six, seven or eight data bits; parity option 4021 enables the transmitter to generate and send a parity bit with each character (thus allowing transmission of characters as long as nine bits including parity) and enables the receiver to check parity. The various characteristics are all selectable separately for the two interfaces by means of jumpers on the board. Transmission and reception can be timed by a clock in the local data set or by an internal clock in the controller (option 4020) for use with an externally clocked modem or a data link that is operated without a modem.
All transfers between controller and memory are in full words containing two characters right-justified in each half word; eg 6-bit characters would be in bits 2-7 and 10-15 of a memory word. The transmitter takes two characters from the appropriate bits of each word from memory and transmits them, first the right and then the left. The receiver assembles each pair of characters into the appropriate bits of a word, right to left, for storage in memory. Characters are transmitted and received serially with the least significant bit first
(ie bit 15 and bit 7).
Receiver
To set up the receiver to handle incoming data, the program must specify a sync character, supply an initial address to the IS-bit address counter, and either supply a specific (twos complement) negative word count to the 12-bit word counter or specify a termination character and a word count large enough (eg zero) to receive the entire message.
7-1
The receiver uses five 10 transfer instructions, one of which includes the status bits for the automatic answering feature. Busy and Done are controlled or sensed by bits 8 and 9 in all 10 instructions with device code 40. Interrupt Disable is controlled by interrupt priority mask bit 8. For convenience, the mnemonic REC is used in representing the instructions, but it is not recognized by the assembler; the programmer must define his own mnemonics.
DOA -,REC Data Out A, Receiver
o
1 ACo
1o
Fo o o o o
I I
o 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Define the sync character as equal to the contents of AC bits 0-7 and the termination character as equal to the contents of AC bits 8-15. Perform the function specified by F.
DOB -,REC Data Out B, Receiver
I
0 1 1 AC 1o o
Fo o o o o
o 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Load the contents of AC bits 1-15 into the receiver address counter, and perform the function specified by F.
DOC -,REC Data Out C, Receiver
o
1 1 AC 1 1o
F I 1o o o o o
o 2 3 4 5 6 7 8 9 10 11 12 13 14 IS
Load the contents of AC bits 4-15 into the receiver word counter, and perform the function specified by F.
DlA -,REC Data In A, Receiver
I
0 1 AC Io o
F Io o o o o
o 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Read the status of the receiver AC bits 11-15 as shown, and perform the function specified by F. Clear AC bits 0--10.
CARRIER DATA SET RING RECEIVER RECEIVER
ON READY INDICATOR TUvtlNG ERROR PARITY ERROR
10 11 12 13 14 IS
Bits 11-13 are for the automatic answering feature described at the end of this section.
7-2
11 A carrier is being received from a remote station.
12 The local data set is connected and is capable of handling data.
13 A ringing signal is being received from a remote station.
14 The data channel has failed to respond in time to a request for access by the receiver and incoming data has been lost.
15 The parity option is installed and a character with inGorrect parity has been received.
DlB -,REe Data In B, Receiver
I
0 ACo
F Io o o o o
o 2 3 4 5 6 7 8 9 10 II 12 13 14 15
Read the present contents of the receiver address counter into AC bits 1-15, clear AC bit 0, and perform the function specified by F.
Setting Busy causes the receiver to monitor the incoming bit stream continuously until it successively receives two of the sync characters defined by the program. This synchronizes the receiver to the bit stream.
It then ignores additional sync characters until some other character is received, at which time it begins assem-bling pairs of characters into words for transmission to the memory locations specified by the address counter.
Since reception is serial the data channel has one bit time in which to respond to a request before information is lost; if the channel is late, Timing Error is set but reception continues. If the receiver is so configured, Parity Error sets if a character with incorrect parity is received.
When the termination character defined by the program appears in the input, the receiver accepts one more character, stores the final word (one or two characters) in memory, and terminates rec¢!ption. In a message containing an odd number of characters, the final word has the last character on the right, garbage on the left. If the termination character does not appear, reception ends automatically when the word counter overflows. In either case, at termination the receiver clears Busy and sets Done, requesting an interrupt if Interrupt Disable is clear.
Transmitter
To set up the transmitter to send data, the program must supply an initial address to the IS-bit address counter and a (twos complement) negative word count to the 12-bit word counter.
The transmitter uses four TO transfer instructions, one of which reads a single status bit. Busy and Done are controlled or sensed by bits 8 and 9 in all 10 instructions with device code 41. Interrupt Disable is con-trolled by interrupt priority mask bit 8. For convenience, the mnemonic XMT is used in representing the instructions, but it is not recognized by the assembler; the programmer must define his own mnemonics.
7-3
nOB -,XMT Data Out B, Transmitter
I
0 AC I I ·o o
F Io o o o
o 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Load the contents of AC bits 1-15 into the transmitter address counter, and perform the function specified byF.
DOC -,XMT Data Out C, Transmitter
I
0 AC 1o
Fo o o o
o 2 3 4 5 6 7 8 9 10 II 12 13 14 15
Load the contents of AC bits 4-15 into the transmitter word counter, and perform the function specified by F.
DIA -,XMT Data In A, Transmitter
I
0 AC Io o
F Io o o o
o 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Read the Data Late status into AC bit 15, clear AC bits 0-14, and perform the function specified by F. A 1 read into AC bit 15 indicates that the data channel has failed to respond in time to a request for access, and sync has been lost.
DIB -,XMT Data In B, Transmitter
I
0 ACo
Fo o o o
o 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Read the present contents of the transmitter address counter into AC bits 1-15, clear AC bit 0, and perform the function specified by F.
Setting Busy causes the transmitter to request data channel access for the first word and raise the Request to Send signal. When the local data set returns the Clear to Send signal, the transmitter begins sending the pairs of characters taken from the memory locations specified by the address counter. Since transmission is serial, the data channel has one bit time in which to respond to a request before sync is lost; if the channel is late, Date Late sets, transmission ceases, Busy clears and Done sets, requesting an interrupt if Interrupt Disable is clear.
7-4
If all is well, the word counter overflows as the last word is received from the channel; overflow clears Busy and sets Done, requesting an interrupt if Interrupt Disable is clear, even though the transmitter has one more word to send. This provides two character times for the program to supply a new initial address and word count and restart the transmitter without losing sync. If the transmitter is not restarted within this time, the Request to Send signal to the data set is dropped, and sync must be reestablished before further data transmission can take place.
Automatic Answering
The controller includes equipment that allows the computer to answer incoming calls if the local data set is so configured and operates with EIA standard levels. For this the program makes use of bits 11-13 of the status word read by the DIA for the receiver. Bits 11 and 12 give the status of the communications circuit and the local data set: bit 11 indicates that a carrier is being received from the remote station; bit 12 indicates that the local data set is connected and is capable of handling data. The program detects a ringing signal from a remote station by periodically examining bit 13, the Ring Indicator. The program answers a call by sending a Data Terminal Ready signal to the local data set; the program must also dismiss the call when completed. The program answers and dismisses a call with the following instruction, which uses the transmitter device code.
DOA -,XMT Data Out A, Transmitter
I
0AC
Io
1o
FI 1
o o o o
o 2 3 4 5 6 7 8 9 10 11 12 13 14 IS
If AC bit 15 is 1, send a Data Terminal Ready signal; if AC bit 15 is 0, terminate the Data Terminal Ready signal. (Perform the function specified by F.)