The design and architecture of the arithmetic unit consisting of the standard functional units, the non-standard functional units, and the elementary functional units are intro-duced and applied to the floating-point accelerator and the reconfigurable streaming floating-point processor. The summaries of this chapter conclude as follows.
• The unified micro-rotations of the double-rotation and triple-rotation CORDIC methods are considered. The design and architecture of the two unified micro-rotations are pro-posed in the pipeline, and investigated based on the basic components, i.e. shifters, CSAs, SDAs, and multiplexers. They are modelled, verified byVHDL, and synthe-sized based on the Xilinx Virtex5 FPGA. Their synthesis results are compared with the unified micro-rotation of the conventional method in terms of performance and efficiency.
• The algorithm, design, and architecture of the high accuracy CORDIC core are introduced.
The algorithm applies the double-rotation method in the normal accuracy and the triple-rotation method for the high accuracy. The algorithm can be reconfigured to perform the CORDIC computation in the circular, hyperbolic, and linear coordi-nate systems by changing the configurable variables at runtime. The timing model, which can be used to investigate the computational latency of the high accuracy CORDIC core, is introduced. The comparison of the published CORDIC methods, i.e. the redundant double-rotation method and2D-Hoseholdermethod, with the pro-posed methods is described in the time and area models. The comparison results illustrate that the proposed non-redundant double-rotation methods provide better time efficiency than the redundant double-rotation and2D-Householder. In addition, the proposed double-rotation method is extended to vectoring mode and also un-employed to use on-line constant scaling factor computation. The area efficiencies of the three methods have similar values due to consuming the same number of ba-sic components. The proposed triple-rotation is evaluated to demonstrate the time and area efficiencies. However, its time efficiency can be improved by increasing the pipeline stages or by enhancing the performance of the adder.
4.8 SUMMARY 129
• Two data conversion algorithms, i.e. the Floating-to-Fixed Algorithm and the Fixed-to-Floating Algorithm, are proposed, where they are used to convert data from floating-point to fixed-floating-point and fixed-floating-point to floating-floating-point.
• The design and architecture of the accelerator and the reconfigurable streaming processor are introduced for the case studies. The main purpose of the accelerator is to accelerate the computation of a main processor while the reconfigurable streaming proces-sor is designed specifically for computing the streaming data. However, the two processors are designed to support the floating-point computation, where the basic operations, i.e. the adder/subtractor, the product-of-sum, and the sum-of-product, are performed in floating-point format, whereas the elementary functions built by CORDIC in fixed-point format.
Chapter 5
Verification on the Closed-Loop Control System for Heavy Ion Synchrotron
Application
Contents
5.1 System Background . . . 132 5.2 Beam Phase Control . . . 133 5.3 Phase-Magnitude Computation . . . 134 5.3.1 State-of-the-Art . . . 134 5.3.2 Architecture for Phase-Magnitude Computing . . . 134 5.3.3 Verification and Simulation . . . 137 5.4 Summary . . . 146
The beam phase and magnitude detector employed in the closed-loop control system for heavy ion synchrotron application is applied for verification of the proposed CORDIC methods. An overview of the closed-loop control system is described; afterwards algo-rithm, design, implementation, and simulation of the digital phase and magnitude detec-tion module is discussed. The sequential index extension method is used for convergence range extension. The design of the digital phase and magnitude detector is modelled and simulated based onVHDL hardware description language. The simulation result based on the actual digital signals of the closed-loop control is compared with Matlab/Simulink ideal result in order to verify the proposed CORDIC’s computation.
131
DDS
Cavity Beam Phase
Monitor
Bandpass Filters Phase and Magnitude Detectors Reference
DDS ω+noise MB+noise
Central Control System
Gap Voltage
Beam position
Target Magnitude
MB
ωDDS
ωDDS ωR,RF
Analog Pre-processing Beam
D-Gap D-Beam
DSP
FPGA
Fig. 5.1: Block diagram of the closed-loop control system for heavy ion synchrotron.
5.1 System Background
In antiproton and ion research, several synchrotrons and storage rings are used for many differential nuclear physic and material sciences. These machines in general deal with longitudinal oscillations of the particle bunches. Longitudinal bunch oscillation can be vi-sualized by beam signals, where the beam current is injected in versus time. For bunched beams, the beam signal consists of a sequence of pulses due to the individual particle bunches. In normal cases, the pulses will generate a constant width beam signal. Acceler-ation process leads to beam signals with decreasing time periods of the pulses. The har-monic number h describes the number of bunches circulating in the synchrotron. Thus, every hth pulse in the beam signal corresponds to the same particle bunch. Different modes of coherent longitudinal beam oscillations may occur due to an initial mismatch or to intensively dependent effect. These oscillations are characterized by their mode number m and n [60] and take place at the characteristic synchrotron frequency, which depends on the system state (more precisely, on the magnitude flux derivative, acceler-ating voltage, and particle energy). In order to eliminate undesired dipole oscillations, a beam phase control system has been devised, which was initially designed to deal with in-phase dipole oscillation (m=1, n=0) only [61]. The addition of amplitude detectors is intended to make it suitable for damping higher-order modes [60] [67].
The closed-loop control system for damping coherent dipole modes of oscillation is implemented by digital components like field programmable gate arrays (FPGAs) and digital signal processors (DSPs), due to flexibility, modularity and scalability for changing the control-loop parameters. The block diagram of theDSPsand FPGAscombination is presented in Fig. 5.1. The DDS unit generates an RF signal with angular frequencyωR,RF+