rate was less than 0.5 nm/min.
3.2.1 Chemical surface cleaning
Surface cleaning is chemically performed and follows standard procedures developed at the WinFAB platform in UCL. To ensure a perfect clean surface out of any carbonated compounds or oxides, Piranha (H2O2:H2SO4, 5:2) bath for 10 min followed by 60 sec dips in hydrofluoric acid (HF 2%) bath are processed. The samples are extensively rinsed for 10 min with DI water between each bath and at the end of the cleaning process. A hydrophobic silicon surface, visually observable, is obtained after the chemical treatment, which is a clue of a H-terminated oxide free surface. In the presence of a thicker silicon dioxide layer (e.g.: PECVD SiO2) a buffered hydrogen fluoride (BHF) bath is performed instead to reduce the silicon dioxide thickness.
3.2.2 Sample back-contacting
This step is only required when electrical measurements are carried out to characterize the front contact. Indeed, any contact on a lowly doped silicon will lead to the formation of a non-ohmic Schottky contact. For instance, in the beginning of the thesis, In-Ga eutectic has been tested as back contact material for electrical measurements. However, impedance measurements highlight the presence of two semi-circles, which can be associated to the presence of two rectifying contacts: one on the front and one in the back of the silicon (Figure 3.5). The problem can be solved by the diffusion of phosphor at high temperature into the silicon, which leads to the creation of a n-rich region not thicker than few µm. The n-rich region suppresses a rectifying contact to be formed. TLM measurements have carried out as well on non-doped oxide free n+-Si surface and oxide free n-Si surface as presented in Appendix A.1. The results show that the superficial diffusion of Phosphor in n-Silicon helps to suppress rectifying junction and to obtain contact resistance in the 1 Ω cm2 range. In addition, impedance spectra only provide one semi-circle, confirming that the diffusion of phosphor leads to the formation of an ohmic back contact (Figure 3.5). Moreover, as measured at UCL, symmetrically enriched silicon wafers provide a charge carrier life-time of 500µs. It proves that, in addition to suppressing barrier height, the process also passivates the surface of the back-contact, which is compatible with solar cell application.
The process to create an ohmic back contact can be detailed as following:
The native oxide is chemically removed following the procedure described in previous part.
A thick sacrificial silicon dioxide layer (∼150µm) is deposited by PECVD on one side of the sample.
Phosphor diffusion in silicon is realized at 900°C for 5 min in a furnace under nitrogen on the unprotected side of the sample.
The chemical baths are performed again to remove the as-grown oxide.
Im(Z)
Re(Z) In-Ga Eutectic Non scratched back contact Scratched back contact
Im(Z)
Re(Z)
Ph. diffusion back-contacting Exp.
Fit
Figure 3.5: Nyquist representation of EIS measurements for In-Ga eutectic back-contacting (left) and for phosphor diffusion back-back-contacting (right). Fits (dotted lines) are attempted with electrical equivalent circuits including exclusively pure capacitive and resistive elements. The comparison of the measurements with the fits highlights that In-Ga eutectic fails to create an ohmic back-contact. On the contrary n+ back contact obtained by phosphor diffusion on one side of the silicon helps to provide a single semi-circle where the fit gives a reasonable good result, suggesting the back contact is ohmic and so there is only one rectifying junction (the front contact).
BHF bath is then performed to remove the poly-silicon-glass formed during the phosphorus diffusion step. Additional time is required to remove completely the thicker sacrificial PECVD SiO2 layer. The BHF bath lasts until the interference fringes due to the thick silicon dioxide layer are visually not observable. The sample is then abundantly rinsed in de-ionized water.
3.2.3 SiO
2thermal growth
Silicon dioxide is a widely studied material in MIS technologies. It has the advantage to be easily produced when a silicon substrate is oxidized. Also its use on the silicon surface enables to obtain a lowly defective interface particularly after hydrogen passivation. Therefore, along this thesis, the SiO2
layer is thermally grown in a furnace in the WinFAB platform at UCL but surface passivation with atomic hydrogen is realized in the Daisy-MAT system at TU-Darmstadt (see Section 3.2.4). However, particular procedures have to be followed to produce a high quality silicon dioxide layer, especially:
Cross-contamination from other elements, e.g.: metal, must be avoided.
An abrupt transition between silicon and silicon dioxide might be desired to reduce the number of defective site, in particular uncoordinated silicon bonds, at the Si/SiO2interface, which can act as interface trap level.
The two requirements above aim at reducing defective states at or near the Si/SiO2 interface. Indeed, defect levels can act as recombination centers for
minority charge carriers, could modify the charge transfer mechanism through the interface and pin the Fermi level of the silicon to an undesired position.
Thus, it has been assumed that the silicon dioxide layer should be grown on an oxide free silicon wafer in a well controlled condition. Therefore, the as-delivered silicon wafer is first cleaned following the chemical bath recipe described in section 3.2.1. Then, a thin silicon dioxide layer is thermally grown in the WinFAB Koyo VP1000 furnace in dry gas (nitrogen or nitrogen/oxygen mixture). The program of the process is basically made of four steps as represented in Figure 3.6:
the sample is kept at 700 °C for 30 min in dry nitrogen to homogenise the temperature in the furnace and purge the chamber.
the temperature in the furnace is ramped up in dry nitrogen until the annealing temperature is reached.
the annealing temperature is held on for a desired period of time. During this period the annealing atmosphere can be selected between pure nitrogen and a nitrogen/oxygen gas mixture.
the temperature is ramped down from the annealing temperature to 700
°C in dry nitrogen.
In general, one cycle takes approximatively 2 hours. Although a high quality silicon dioxide layer can be obtained at high temperatures, the silicon dioxide layer has to be thin enough (<2.5 nm) to allow tunnelling of the charge carriers.
To obtain a thin tunnelling SiO2 layer becomes more difficult to achieve with increasing annealing temperature, but after furnace calibration (see Chapter 11), it has been assumed that the desired SiO2layer could be obtained at 1000
°C with no annealing period in dry nitrogen. It is believed that the oxygen participating in the SiO2 growth process originates from oxygen desorption from the furnace wall during the thermal cycling. An approximatively 2.3 - 2.5 nm silicon dioxide layer is obtained with this thermal program on top of silicon, which is compatible with charge tunnelling. The Si/SiO2base substrate is then later stored in air.
Figure 3.6: Left: Typical furnace profile. Right: Profile used to obtain a thermally grown tunnelling SiO2 layer at 1000 °C on silicon during this thesis.
3.2.4 In-situ plasma cleaning and hydrogen surface passivation
A hydrogen plasma source (Tectra Gen2 Hybrid Atom/Ion Source) was used for both surface cleaning and passivation of the Si/SiO2 samples as detailed in Chapter 11. Atomic hydrogen is obtained by cracking dihydrogen molecules in the plasma chamber set on atomic mode for which the current was set to 30 mA and the gas pressure to 0.2 mbar. The hydrogen cleaning step is realized at about 250°C for 10 min and allows to remove efficiently carbonated contaminants and possibly hydroxilated compounds, which are present on the surface because of air exposure of the Si/SiO2 samples. An additional 45 min hydrogen plasma exposure is necessary at higher temperature for the hydrogen passivation step according to reports found in the literature regarding Si/SiO2
passivation [123, 152, 153]. As the temperature range was limited in the setup, the temperature for hydrogen passivation was set to 350°C . To avoid possible hydrogen desorption from the sample, the plasma is maintained until the sample holder temperature reaches∼150°C.
3.2.5 Alumina deposition by ALD
Alumina layers deposited by Atomic Layer Deposition (ALD) have been performed on top of the hydrogen passivated Si/SiO2structure in the DAISY-MAT system at TU-Darmstadt [154]. The alumina layer is obtained by the alternative deposition of TMA (trimethylaluminum) and its oxidation by water.
One ALD cycle consisted in a TMA and water pulse lasting respectively 80 ms and 150 ms, which are separated by an pumping period of 5 min in vacuum.
As the alumina layers have been deposited on the hydrogen passivated Si/SiO2 samples, a low temperature for the alumina deposition was preferred.
The reason, even though this was not proven at this level, is that it would limit the risk of the depassivation of the Si/SiO2 structure. Thus, the temperature during the ALD process was constrained from room temperature to 200°C in this thesis.