--.J 100
I-r-Int Request From Devices
~I ns
Device A Req -L===r~{ ~s---~~~~
175ns Min
f-1 ~s~~-I-I---
lus Min ... 1De~i~;~-R-eq
Update Queue
_____
~t~tr---~IIL---~~~=-~~Device Priority to I/O Data Bus
Lo-Pri (A) Device @ 0' II II
Hi-Pri Device (B) @100' _ _ _ _ _ _ _
...c::r---r=:J... _ _ _ _ _ _
SID @ CPU, Device A
Device B Priority@CPUi---c::==:::r---:---c==:::L--SID @ CPU, Device B
CPU SI D Register
x
"B I R Load, Aborted I nstr
r-
2.4 us to 1 st. I nstruction of I nterrupt Routine ---MODCOMP Update Queue Timing for Service or Data Interrupt--l
200nsr---CPU Clock
1~
Clock 2
I
-1
100Req~est from ns • A Req
DeVices - - - Device B Req
I..
800ns-I
Update Queue , , , ,
Device Priority to
I/O Bus _ _ _ '0-1 ---~~ _ _ _ _ _ _ _
Lo-Pri Device (A) @O'
__________ JT---LL ________ _ Hi-Pri Device (B) @100'
__________________ ~~---LI~I ______ __
Device B Pri @ CPU Device B SI D @ CPU Device A SID @ CPU
CPU 51 D Register _ _ _ _ _ _ _ _ _ _ _ _ _ ---1:1 r;:1
B~---MODCOMP DMP Queue Update Timing
Signal Levels
The signal levels at the cable driver/receiver interface to the controller logic are:
Logic 0: 2.4 to 5.5 Volts Logic 1:
o
to 0.4 Volts Except 10lCB which is inverted.The cable diagram illustrates a MODCOMP II I/O Bus system with the driver/receiver sets and the associated termination network.
The I/O Clock (IOCLKN), a 5 MHz square wave, is
dis-tributed on the I/O bus for general purpose use in the controllers.
When the 10lCB (Initial Condition Bus) comes true, each controller wi II normalize (not busy, no interrupt or DMP Requests, no interrupt enabled, device normalized, etc.).
This signal is present if the CPU power is going down and is present to normalize the system when power is returned to the CPU and when the master clear switch on the CPU console is depressed.
All signals are ground true except 101CB. This allows each controller to recognize the absence of a current sink in the CPU and normalize when CPU power is absent.
. - - - - - - - - - I r - - - - - - - - - - - - - - - - - I
, - - - ,
1MAX SOURCE CURRENT-2MA
~»_1_r_~~r_-+---~--_4-~---_4-~--~-4~~--~~~-+_----1_----~--+_---~--+_---~-4~~1 ~~~Vy--
LInput/Output Cable Diagram
GND
Interfacing to the General Purpose Controller
The general-purpose controller provides the means for customer implementation of a standard interface between the cable driver/receiver set and special device controllers.
The general purpose controller includes all the general interfacing logic required to connect an I/O device to the I/O cable. It contains an available work area where data buffer registers, setup registers, input status logic and special control logic can be implemented. I t also provides the logic for two I/O interrupts and a DMP channel interface. The controller generates the timing pulses for transferring data, commands and status into and out of are available. Detailed descriptions of the internal jumpers required are described in the Peripheral Controller Manual.
Data transfers are controlled by two signals from the general purpose controller. One signal (Output Data Com-mand) is a strobe pulse used to output a data word to a
An additional feature of the general purpose controller is the interlocking logic for device dependent functions.
A busy signal from the work area is required to enable and disable the interlocking function. The interlocking function is used to prevent a device from receiving motion commands, caused by program errors, during a period in which the device is performing a previous motion command.
For setup operations, the command instruction causes a gating signal that will load the command register in the work area. This pulse only occurs if the busy signal is false. For more complex operations, several sub-func-tions of the commands are available and are discussed
Logic diagrams and physical layout drawings are provided in the Peripheral Controller Manual as a guide to imple-menting all of the logic functions common to most bi-directional devices. 54 integrated circuit connectors with wirewrap pins are provided for the implementation of this logic together with the integrated circuits required.
I n addition, a total of 89 unassigned dual-in-line integrated circuit connectors are provided on the same printed circuit card. These may be used for the custom logic required for each controller, in addition to that portion of the general purpose logic implemented.
The general-purpose controller is packaged on a 7" x 14Y:!' printed circuit card. It contains dual in-line integrated circuit connectors for all logic circuits. Power and ground are distributed by printed wiring. The number of con-nectors available for custom wiring is:
POWER AND GROUND
PINS CONNECTORS CONNECTED
14 64 Yes connectors and standard I/O cables are used for connecting peripheral devices to the controller. The 16-pin connectors which are not tied to the power or to ground are used for cable terminating resistors.
Interfacing Through the Modular Bus Control
Features
The MODCOMP I and II computers provide a unique input/output control capability that allows control of the system resources from a ROM or hardwired control logic.
An external interface is provided not only for data lines,
but also for the micro-control functions in the processor. Modular Bus are available externally. Therefore, data can be moved in any desired manner between input/
output, register file and main memory. This capability not only includes that of transferring data in and out of memory on a cycle-stealing basis, but it also provides far more flexibility than a conventional Direct Memory Access. The external controller can generate instructions to cause the processor to operate arithmetically or logically on an input or output bit, byte, or word as part of the transfer process. I n addition, since input/output instruc-tions can be generated externally, data can be transferred from one external device to another device, with or without CPU processing, all under external control.
General Description
Source liB" Control
Three lines are provided for source B control, one enable registers, memory address, memory data, adder register or data out. source and destination logic.
2. Generate a memory request strobe any time after the source and destination logic.
2. Generate a memory request strobe any time after the memory address register is loaded.
3. Load the memory data register using the MBC source and destination logic.
4. Generate a write request strobe.