The R/C Address Mux consists of two quad, 2 to 1 mul tiplexers (data selectors). On the inputs are the 12 low-order bits (MAO - MA11) of the 14-bit output of the Address Selector Mux. These
12 bits are enabled through the R/C Address Mux alternately; MAO - MAS on the first select and MA6 - MALL on the second select;
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six bits at a time, by SELRAS. SELRAS is enabled by RAS, the term which strobes the first six bi ts of RAM address into the RAMs. Stated simply, when SELRAS (RAS) is active, the first six bits are strobed through, and when SELRAS is not active (CAS active), the second six bits are strobed through. This places the 6-bit row address on the RAM address lines when RAS is true, and the 6-bit column .address on the RAM address lines when CAS is true.
Page Select (Schematic Sheet 3)
This demul tiplexer/decoder decodes the upper two address bits (MA12 and MA13) of the Refresh RAM address from the Address Selector for memory page selection. The coding is as follows:
MA12 MA13 Page
-
-'0 0 1,2
0 1 3,4
1 0 5,6
1 1 7,8
Data Buffer And Latches (Schematic Sheet 5)
The Data Buffer consists of two, bidirectional·, tri-state bus transceivers and a 2 to 1 multiplexer. Data from the RAMs to be driven to 'the Data Bus is asserted.as RMOOO • RHD07 and, by selecting the drivers, is driven to the bus as DO - 07. If data from the Data Bus is to be written into the RMS, the receivers are selected and the bus data (DO - 07) is routed to the RAMS as RMDIO - RMD17. The term which selects the direction of data through the buffers is BR/W.
The Data Latches consist of two, quad D-type flip-flops. The data from the RAMs to be displayed by the monitor is asserted on the inputs as RHOOO - RHD07. The output data to the Character Generators is DATAO - DATA6. This 7-bit data block defines a stored character in the Character Generator which is to be 'displayed on the CRT! Also, output from the latches is the inverse DATAO - DATAr. This information, along with a portion of the positive-t.rue output (OATAO - DATA7) is used to establish the display at1;·ributes.
Character Generators (Standard And Alternate) (Schematic Sheet 6) The Character Generators are EPROMs programmed with 128 dis-playable characters (upper and lower case) in the ASCI I code.
The character is specified by DATAO - DATA6 and the actual raster line count is contained in LCO - LC3. The ASCII char-acter information is contained in the output byte, CGO - CG7.
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The chip select term is ALTNCG, which selects either the Standard or Alternate character generator. The Standard gen-erator is the one normally used. The Alternate is used for for.eign language or special character generation.
Video Logic (Schematic Sheet 7)
This logic group conditions the binary data containing the character and attributes of the character and the display into a form (COMPOSITE VIDEO) capable of being displayed on the CRT.
Also available in this section are the sync signals (HSYNC and VSYNC) needed to synchronize the display with the information to be displayed.
The COMPOSITE VIDEO is appl ied directly to the CRT.
signals are sent to the monitor electronics. The sync The character generator information (CBO - CG7) is asserted on the parallel inputs to an 8-bit shift register. They are loaded by SHLOAD and clocked out the serial output as CVID.
The Null Detect circuit gives the user the option of displaying or inhibiting the display of a null character. This circuit decodes DATAO - DATA6 to make that determination depending upon the state of the DISNUL switch~
DATA7 is used by the Video Logic to produce the PROTECT BIT (PROBIT) signal. If a character is to be displayed in a pro-tected area of the CRT, the seventh bit of the character code is set high. This causes the monitor to display that character at a reduced intensity.
6.3.5 Keyboard Section (Figure 6-9)
The Keyboard provides the operator interface between the ADM-42 and the remote computer. It is a detachable, 118-key keyboard containing alphabetic and numeric characters, symbols, and special keys wh ich con trol the ADM-42 operations. The 16 special-function keys can
be
used with the SHIFT key to produce 16 additional functio~.The Keyboard section consists of the keyboard matrix, a Peri";' pheral Interface Adapter (PIA), an 8 to 1 mux, a 4 to 16 de-coder, timing logic, and associated indicator lamps.
Keyboard Matrix (Schematic Sheet
The keyboard matrix consists of a 16 x 8 (128 intersections) matrix with 118 of the intersections being occupied by the ADM-42 character (alphabetic and numeric), symbol, and control keys. The MPU generates a binary count cycle (scan) and routes
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it to the PIA as DBa - DB 7 • The PIA genera tes KBO - KB6 and rQutes the lower four bits (KBDO - KBD3) to the 4-to-16 decoder and the upper three bits to the 8-to-1 mux. Using the decoder and the multiplexer the MPU (via the PIA) scans each inter-section of the matrix. If a key is pressed, the next scan that polls that intersection senses the key and generates STROBE at that "X" and lIy" coordinate address. STROBE is routed to the PIA, stops the scan, locks the address at STROBE time, and produces DEBTRG (Debounce Trigger). DEBTRG triggers the NE 555 Timer and 10 ms later, DEBDLY (Debounce Delay) is produced.
If the key is still sensed by the time DEBDLY comes true, the address of that key is decoded as to the character in the Look-Up table located in the system memory and the appropriate ASCII. character code is generated to the Character Generator (the Video Section), to be displayed. If, however, the key is not sensed at DEBDLY time, the look-up is aborted and the scan is restarted.
Peripheral Interface Adapter (PIA) (Figure 6-10)
The PIA is a universal interface device that controls the transfer of data from the keyboard to the CPU and the monitor.
The binary count cycle (scan) is received via the data bus as DBa - DB7). The PIA generates the actual scan code, KBDO -KBD3 (X axis) and KBD4 -KBD6 (Y axis) for the keyboard matrix.
When a key is sensed (or suspected), STROBE is generated, after having stopped the scan and stored the address present at the
time that STROBE came true. After 10 ms, DEBDLY is returned to the PIA, and if STROBE is s t i l l true, the stored address is routed to the MPU as DBO - DB7 and decoded into the appropriate ASCII character code from the Look-Up table in System Memory.
It is then routed to the video section where it is displayed on the monitor CRT.
If STROBE is not true when DEBDLY is returned to the PIA, the stored address is released and the keyboard scan is continued.
Four to Sixteen Decoder
~.
This device does a binary decode of the lower four bits (KBDO -KBD30 of the ~can count furnished by the PIA such that one output line is selected each time the 4-bit binary number is incremehted, placing a low level on the corresponding vertical matrix line.
Eight-to-One Multiplexer
This device does a binary decode of the three upper bits (KBD4 - KBD6) of the scan count such that one of the eight horizontal matrix lines is addressed each time this 3-bit
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4-TO-16 KBDg-KBD3 DECODER
DBg-DB7 DC)J-DC16
~ PIA