ROP Tests

The following sections contain test descriptions for the Raster Operation Processor (RaP) chips on the CG30 Board.

6.3.6.1 Registers Tests

The following tests verify that the ROP chips are accessable and functioning correctly.

6.3.6.1.1 Test 69 - Single Plane Registers Test

This test verifies that the ROP registers on the CG30 board can be accessed and checks these registers for data retention. Each register is tested for a series of patterns which are written, read back and compared. The test is performed on each plane's ROP chip.

Registers tested are:

1. Destination Register 2. Source 1 Register 3. Source 2 Register 4. Pattern Register 5. Mask 1 Register 6. Mask 2 Register 7. Shift Value Register 8. Function Register 9. Width Register 10. OP Counter Register 11. Flag Register

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

Where:

ROP TESTED Register RIO write access error ROP Register

=

^{ROP REG}

Slot ~ SLOT

RIO address = XXXXXXXX

Data error in ROP TESTED Register ROP Register = ROP REG

Slot = SLOT

RIO address = XXXXXXXX exp = EE

act AA xor = 00

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SLOT Slot number of CG30 board under test

ROP TESTED Name of ROP under test

ROP REG ROP register under test

XXXXXXXX RIO address of ROP register under test

EE Expected value of register

AA Actual value read from register

00 XOR of expected and actual values 6.3.6.1.2 Test 70 - All Planes to Single Plane Registers Test

This tests verifies that the ROP registers on all ROP chips may be simultaneously written. Each ROP register on the All ROP register is written, each plane ROP chip register is then read and the data compared with the value that written to the All ROP register.

Registers tested are:

1. Destination Register 2. Source 1 Register 3. Source 2 Register 4. Pattern Register 5. Mask 1 Register 6. Mask 2 Register 7. Shift Value Register 8. Function Register 9. Width Register 10. OP Counter Register 11. Flag Register

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

All Planes Rap Register RIO write access error Rap Register ^£ Rap REG

Slot

=

SLOT

RIO address = XXXXXXXX

Rap TESTED Register RIO read access error Rap Register = Rap REG

Slot '"" SLOT

RIO address = XXXXXXXX

Data error in Rap TESTED Register Rap Register

=

Rap REG

Where:

Slot = SLOT

Write RIO address = WWWWWWWW Read RIO address = ^RRRRRRRR

exp EE act AA

xor 00

SLOT Slot number of CG30 board under test Rap TESTED Name of ROP under test

Rap REG ROP register under test

wwwwwwww RIO address of ROP register written RRRRRRRR RIO address of ROP register read EE Expected value of register

AA Actual value read from register 00 XOR of expected and actual values 6.3.6.1.3 Test 71 - BTLA Mode Single Plane Registers Test

This test verifies that accesses to the ROP chips using the Byte Transfer Load Alternate (BTLA) mode follows the specified format. In this access mode the data path is tested for a series of patterns for each individual ROP chip.

A series of patterns are written, read back, and then compared in order to verify that the correct action took plane.

Registers tested are:

1. Destination Register 2. Source 1 Register 3. Source 2 Register

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4. Pattern Register 5. Mask 1 Register 6. Mask 2 Register 7. Shift Value Register 8. Function Register 9. Width Register 10. OP Counter Register 11. Flag Register

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

Where:

SLOT Slot number of CG30 board under test ROP TESTED Name of ROP under test

ROP REG ROP register under test

wwwwwwww RIO address of Rap register written

RRRRRRRR RIO address of Rap register read PP Pattern written to register EE Expected value of register

AA Actual value read

00 XOR of expected and actual values

6.3.6.1.4 Test 72 - BTLA Mode All Planes to Single Plane Registers Test

This tests verifies that the ROP registers on all ROP chips may be simultaneously written using Byte Transfer Load Alternate mode. Each ROP register on the All ROP register space is written, each plane's ROP chip register is then read and the data compared with the value that written thru the All ROP register space.

The plane mask register affects both read and write operations in pixel mode. Only planes whose corresponding bit in the Plane Mask register is set will be modified by write operations.

This condition is checked by writing a series of patterns for all combinations of enabled/disabled planes in the Plane Mask register.

Registers tested are:

1. Destination Register 2. Source 1 Register 3. Source 2 Register 4. Pattern Register 5. Mask 1 Register 6. Mask 2 Register 7. Shift Value Register 8. Function Register 9. Width Register 10. OP Counter Register 11. Flag Register

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

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SLOT Slot number of CG30 board under test

P Number of Plane under test ROP TESTED Name ofROP under test ROP REG ROP register under test

WWWWWWWW RIO address of ROP register written

RRR.RRRRR RIO address of ROP register read

PP Pattern written to register EE Expected value of register AA Actual value read from register

00 XOR of expected and actual values

v

6.3.6.2 Mode Tests

The following tests verify the operation of the ROP chips in each operation mode.

6.3.6.2.1 Test 73 - Mode-O Read Access Test

This test verifies that read accesses to the frame buffer using the ROP mode address space during ROP mode 0 in fact result in a load of the ROP destination register from the frame buffer.

This test verifies the address and data paths between ROPs and the frame buffer. The test performs a simple sequence of writes to the frame buffer in plane mode, reads from the ROP mode space, and assures that the ROP destination register gets loaded with the pattern that was written in the frame buffer.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

RIO read access error

during ROP Mode-O Frame Buffer Access Slot

=

SLOT Plane

=

PLANE

RIO address

=

RRRRRRRR RIO write access error

during PLN ACC TYPE

Slot

=

SLOT Plane

=

PLANE RIO address = PPPPPPPP

ROP Destination Register RIO read access error Slot

=

SLOT Plane

=

PLANE

RIO address = XXXXXXXX

ROP Destination Register data error

Where:

during ROP Mode-O Read Access to Frame Buffer Slot = SLOT Plane = PLANE

ROP Mode Access RIO address = RRRRRRRR Plane Major Access RIO address

=

PPPPPPPP

ROP Destination Register RIO address

=

^XXXXXXXX

exp EE act = AA xor

=

00

PLN Ace TYPE Name of Plane under test

SLOT Slot number of CG30 board under test PLANE Plane under test

RRRRRRRR pppppppp

xxxxxxxx

EE

AA 00

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ROP Mode RIO address Plane Major RIO address

RIO address of ROP register under test Expected value of register

Actual value read from register XOR of expected and actual values 6.3.6.2.2 Test 74 - Mode-l Read Access Test

This test verifies that read accesses to the frame buffer using the ROP mode address space during ROP mode 1 results in a load of the ROP destination register from the frame buffer. This test verifies the address and data paths between ROPs and the frame buffer. The test performs a simple sequence of writes to the frame buffer in plane mode, reads from the ROP mode space, and assures that the ROP destination register gets loaded with the pattern that was written in the frame buffer.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

RIO read access error

ROP Destination Register data error

during ROP Mode-l Read Access to Frame Buffer PLANE Plane under test

RRRRRRRR ROP Mode RIO address PPPPPPPP Plane Major RIO address

XXXXXXXX RIO address of ROP register under test EE Expected value of register

AA Actual value read from register

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00 XOR of expected and actual values 6.3.6.2.3 Test 75 - Mode-4 Read Access Test

This test verifies that read accesses to the frame buffer using the ROP mode address space during ROP mode 4 results in a load of the ROP destination and source registers from the frame buffer. This test verifies the address and data paths between ROPs and the frame buffer. The test performs a simple sequence of writes to the frame buffer in plane mode, reads from the ROP mode space, and assures that the ROP source and destination register get loaded with the pattern that was written in the frame buffer.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

ROP Shift Value Register RIO write access error

ROP Destination Register data error

during ROP Mode-4 Read Access to Frame Buffer

SLOT Slot number of CG30 board under test PLANE Plane under test

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RRRRRRRR PPPPPPPP XXXXXXXX EE

AA 00

ROP Mode RIO address Plane Major RIO address

RIO address of ROP register under test Expected value of register

Actual value read from register XOR of expected and actual values 6.3.6.2.4 Test 76 - Mode-S Read Access Test

This test verifies that read accesses to the frame buffer using the Rap mode address space during ROP mode 5 results in a load of the ROP destination register from the frame buffer. This test verifies the address and data paths between ROPs and the frame buffer. The test performs a simple sequence of writes to the frame buffer in plane mode, reads from the ROP mode space, and assures that the ROP destination register gets loaded with the pattern that was written in the frame buffer.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

ROP Shift Value Register RIO write access error

SLOT Slot number of CG30 board under test PLANE Plane under test

RRRRRRRR Rap Mode RIO ~ddress

PPPPPPPP Plane Major RIO address

xxxxxxxx

RIO address of ROP register under test EE Expected value of register

AA Actual value read from register 00 XOR of expected and actual values -6.3.6.2.5 Test 77 - Mode-6 Read Access Test

TIlls test verifies that read accesses to the frame buffer using the ROP mode address space during Rap mode 6 results in a load of the ROP source register from the frame buffer. TIlls test verifies the address and data paths between ROPs and the frame buffer. The test performs a

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simple sequence of writes to the frame buffer in plane mode, reads from the ROP mode space, and assures that the Rap source register gets loaded with the pattern that was written in the frame buffer.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

RIO read access error

ROP Destination Register data error

Where:

PLANE Plane under test

RRRRRRRR ROP Mode RIO address PPPPPPPP Plane Major RIO address

XXXXXXXX RIO address of Rap register under test

EE Expected value of register

AA Actual value read from register 00 XOR of expected and actual values

6.3.6.2.6 Test 78 - Mode-O Write Access Test

This test verifies that write accesses to the frame buffer using the ROP mode address space during ROP mode 0 results in a load of the frame buffer with the correct result for the AND, OR, and XOR logical operations performed by each individual ROP on a series of patterns. This test verifies the address and data paths between ROPs and the frame buffer as well as some basic ROP chip functionality.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

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SLOT Slot number of CG30 board under test PLANE Plane under test

FUNCTION Logical function (AND, OR, XOR)

RRRRRRRR Rap Mode RIO address

pppppppp XXXXXXXX EE

AA

00

Plane Major RIO address

RIO address of Rap register under test Expected value of register

Actual value read from register XOR of expected and actual values 6.3.6.2.7 Test 79 - Mode-l Write Access Test

This test verifies that write accesses to the frame buffer using the Rap mode address space during Rap mode 1 results in a load of the frame buffer with the correct result for the AND, OR, and XOR logical operations performed by each individual Rap on a series of patterns. This test verifies the address and data paths between Raps and the frame buffer as well as some basic Rap chip functionality.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

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SLOT Slot number of CG30 board under test PLANE Plane under test

FUNCTION Logical function (AND, OR, XOR) RRRRRRRR ROP Mode RIO address

pppppppp XXXXXXXX EE

AA

00

Plane Major RIO address

RIO address of Rap register under test Expected value of register

Actual value read from register XOR of expected and actual values 6.3.6.2.8 Test 80 - Mode-2 Write Access Test

This test verifies that write accesses to the frame buffer using the Rap mode address space during Rap mode 2 results in a load of the frame buffer with the correct result for the AND, OR, and XOR logical operations performed by each individual Rap on a series of patterns. This test verifies the address and data paths between Raps and the frame buffer as well as some basic Rap chip functionality.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

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SLOT Slot number of CG30 board under test P LANE Plane under test

FUNCTION Logical function (AND, OR, XOR) RRRRRRRR Rap Mode RIO address

PPPPPPPP Plane Major RIO address

XXXXXXXX RIO address of Rap register under test EE Expected value of register

AA 00

Actual value read from register XOR of expected and actual values 6.3.6.2.9 Test 81 - Mode-3 Write Access Test

This test verifies that write accesses to the frame buffer using the ROP mode address space during ROP mode 3 results in a load of the frame buffer with the correct result for the AND, OR, and XOR logical operations performed by each individual ROP on a series of patterns. This test verifies the address and data paths between ROPs and the frame buffer as well as some basic ROP chip functionality.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

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S LOT Slot number of CG30 board under test PLANE Plane under test

FUNCTION Logical function (AND, OR, XOR) RRRRRRRR Rap Mode RIO address

PPPPPPPP Plane Major RIO address

XXXXXXXX RIO address of Rap register under test EE Expected value of register

AA 00

Actual value read from register XOR of expected and actual values 6.3.6.2.10 Test 82 - Mode-4 Write Access Test

This test verifies that write accesses to the frame buffer using the ROP mode address space during ROP mode 4 results in a load of the frame buffer with the correct result for the AND, OR, and XOR logical operations performed by each individual ROP on a series of patterns. This test verifies the address and data paths between ROPs and the frame buffer as well as some basic ROP chip functionality.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

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PLN ACC SLOT PLANE FUNCTION RRRRRRRR PPPPPPPP XXXXXXXX EE

AA.

00

TYPE Name of Plane under test

Slot number of CG30 board under test Plane under test

Logical function (AND, OR, XOR) ROP Mode

ruo

address

Plane Major

ruo

address

ruo

address of ROP register under test Expected value of register

Actual value read from register XOR of expected and actual values 6.3.6.2.11 Test 83 - Mode-5 Write Access Test

This test verifies that write accesses to the frame buffer using the ROP mode address space during ROP mode 5 results in a load of the frame buffer with the correct result for the AND, OR, and XOR logical operations performed by each individual ROP on a series of patterns. This test verifies the address and data paths between ROPs and the frame buffer as well as some basic ROP chip functionality.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

Solboume Confidential Information - Do Not Distribute PLANE Plane under test

FUNCTION Logical function (AND, OR, XOR) RRRRRRRR ROP Mode RIO address

pppppppp XXXXXXXX EE

AA 00

Plane Major RIO address

RIO address of Rap register under test Expected value of register

Actual value read from register XOR of expected and actual values 6.3.6.2.12 Test 84 - Mode-6 Write Access Test

This test verifies that write accesses to the frame buffer using the ROP mode address space during ROP mode 6 results in a load of the frame buffer with the correct result for the AND, OR, and XOR logical operations performed by each individual ROP on a series of patterns. This test verifies the address and data paths between ROPs and the frame buffer as well as some basic ROP chip functionality.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

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SLOT Slot number of CG30 board under test

PLANE FUNCTION RRRRRRRR PPPPPPPP XXXXXXXX EE

AA 00

Plane under test

Logical function (AND, OR, XOR) Rap Mode RIO address

Plane Major RIO address

RIO address of Rap register under test Expected value ofregister

Actual value read from register XOR of expected and actual values 6.3.6.2.13 Test 85 - Mode-7 Write Access Test

This test verifies that write accesses to the frame buffer using the ROP mode address space during ROP mode 7 results in a load of the frame buffer with the correct result for the AND, OR, and XOR logical operations performed by each individual Rap on a series of patterns. This test verifies the address and data paths between Raps and the frame buffer as well as some basic ROP chip functionality.

Refer to Appendix C if frame buffer configuration table contains multiple CG30 boards and the test is prompted.

Possible errors detected by this test:

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SLOT Slot number of CG30 board under test

SLOT Slot number of CG30 board under test

Im Dokument Bootable/Standalone Diagnostics Manual (Seite 98-129)