?/;-=:::-NMI DISABLED
NOTE
•
tE NMI 0 ENABLEDaHIg301
This jumper is not loaded on the HP27111A, forcing the card to always default to NMI disabled.
Reset Control
. The HP2711lA is reset through PASSPORT with three levels of severity: Power On, Channel, and Device Clear. PASSPOR T, in turn generates two types of reset pulses which are then distributed to the remainder of the HP27111A, RESET- and CLK_RST- {U 14-N4, P3}.
Ordinarily, a Power On reset occurs when power is initially applied to the channel and the HP2 7111 A, in order to initialize the card. A Channel reset may occur at any time and resets all the cards in a particular channel. Device Clear is a selective reset of the HP27111A.
The cause of the latest reset is posted by PASSPORT in the control block following the initialization sequence.
POWER ON RESET.
A Power On Reset is generated when PON+ deasserts.
This form of reset causes both CLK_RST- and RESET- to assert.
All card state information is lost unless the card is configured for secondary power usage and secondary power was not lost.
A typical Power On sequence from the Backplane Adapter's perspective is as follows. When power is initially applied, PON+ is deasserted. When power is stable and PON+ is still deasserted, PASSPORT will assert both CLK_RST - and RESET - to the rest of the card. Both of these signals will remain asserted
very preliminary 7-20
Theory of Operation
as long as PON+ is deasserted. When PON+ asserts, ClK_RST- will"deassert approximately 2SCLK+
cycles after this event. RESET- will remain asserted for approximately 512 more SCLK+ cycles and then will deassert.
While PON+ is deasserted, and power is present and stable, all external pins on PASSPORT will be in the high-impedance state with the the exception, of course, of CLK_RST- and RESET-.
When both CLK_RST - and RESET - have deasserted, the Backplane Adapter is in the following state:
SIGNAL STATE Asserted
Deasserted
High Impedance
Backplane Adapter Power On Status
SIGNAL (none)
Channel signals: ARQ-, NMI-, MVAD-,
BR-Internal signals: OIN+, lINK_EN+, PASSPORT _'NT+, MRQ+,
RESET-,CLK_RST-Channel signals: DEND-, OBYT-, P _CDPO-, P _CDP1-.
P _08[0:15]- . ,
Internal signals: lD[0:15]+, SA[15:1]+, BYTE+, END+. RD-.
WR-. lINK_PARITY[O:1]+
The Backplane Adapter will remain in this state until the Channel or self test firmware controlled by the Processor programs it to behave differently.
The Backplane Adapter will not respond to the Channel until the Channel has taught it a physical address (see control and address).
NOTE
The HP27111A reVISIon code "0" will lose ALL card state information regardless of presence of secondary power. The necessary hardware is present to recover in revision "0". The necessary firmware is not!
CHANNEL RESET.
A Channel Reset is caused when RST- is asserted.
This form of reset causes both CLK_RST- and RESET- to assert.
All card state information is lost during this reset.
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Channel Reset behaviour for the Backplane Adapter is essentially the same as with the Power On reset.
When RST- is asserted by the Channel, PASSPORT will assert both CLK_RST- and RESET- to the rest of the card. Both of these signals will remain asserted as long as RST- is asserted. When RST- deasserts, CLK_RST- will deassert approximately 2 SClK+ cycles after this event. RESET- will remain asserted for approximately 512 more SCLK+ cycles and then will deassert.
While RST- is asserted, a-nd power is present and stable, all external pins on PASSPORT will be in the high-impedance state with the the exception, of course, of ClK_RST-and RESET-.
When both CLK_RST- and RESET- have both deasserted, the Backplane Adapter is in the following state: All of the Backplane Adapter signals will remain in their "power on" state with the exception of the Device Clear Machine which enters the <IDLE> state.
As before, the Backplane Adapter will remain in this state until the Channel or self test firmware controlled by the Processor programs it to behave differently.
DEVICE CLEAR.
A Device Clear is caused when a Channel Write Control[DCL] operation is issued to the address corresponding to the card's physical address.
This form of reset causes only RESET - to assert.
The Device Clear remains in effect until a Channel Write Control[DEN] is issued to the address corresponding to the card's physical address. RESET- will deassert 512 SClK+ cycles after the Channel operation.
The Backplane Adapter's behaviour during a Device Clear is very similar to both the Power On and Channel reset cases. The two exceptions are the preserving of the card's physical address, and the state of the Device Clear Machine.
The card's physical address, stored in PASSPORT, remains valid through the duration of the Device Clear.
Thus the card remains capable of channel communication after the Device Clear, and cannot be
"retaught" a new physical address.
The Device Clear machine differentiates the Device Clear from the other types of resets and relays this state to the rest of the card.
DEVICE CLEAR MACHINE.
The Device Clear sequence is detected externally by the Device Clear Machine which will assert DCL_INT+ to the 80186 Processor. Basically, the machine looks for an instance when RESET- is asserted without an accompanying ClK_RST-.
The Device Clear machine is implemented using part of a 16R4 PAL {U 17}. In describing the state behaviour of the Device Clear Machine, the following group of signals is treated as a vector:
Device Clear State: [DCl_INT+. CLR_WAIT-, Q1+]
very preliminary 7-22
Q1+ is a state output of {U I7} that has no other connections.
Flow charts to illustrate the Device Clear Machine's behaviour follows:
o
Theory of Operation
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very preliminary 7-24
1
1
1
1
Theory of Operation
ARMED- is asserted during a Processor Write to the memory area addressed by PCS[3]-, as shown in the flow chart. DCl INT + cannot be asserted until ARMED- has been asserted. Note that ARMED- is placed in a deasserted state by the main Device Clear Machine entering the < POWERON > state, indicated by the internal signal @POWERON+. Thus any type of reset disarms the Device Clear Mode, including a Device Clear itself. This is because the Processor block needs to check its ability to respond to a DeL each time it is either soft or hard reset.
The main Device Clear State Machine behaviour is then as follows:
Device Clear State: < POWERON >
Out puts :[ClR_ WAIT -]
The DCL machine samples the states of PASSPORT's two reset control lines ClK_RST- and RESET-.
When both reset control lines are deasserted, the machine will enter the < IDLE> state.
The DCL machine now looks for one of three events:
a Device Clear Reset, anon-Device Clear Reset, or
The machine will remain in the <QUEUE> state until ARMED- is asserted or a non-Device Clear Reset occurs, entering the < NMI 1 > and < POWERON > states, respectively.
DCl_INT+ is asserted. The machine will always return to the < POWERON > state at this point, and wait for the Device Clear to complete.
The Processor block is now ready to handle a Device
Device Clear State:<NMI2> operating state of the machine when the HP2711lA is operational.
DCl_INT+ is asserted. The machine will always return to the < POWERON > state at this point, and wait for the Device Clear to complete.
The state of the Device Clear machine is communicated to the Processor block via the ClR_ WAIT - and DCl_INT+ signals. As noted in the state machine description, CLR_WAIT- is asserted when the adapter is in a Device Clear condition. When CLR_WAIT- is deasserted, the adapter is in a normal operational state. Thus, if a DCl_INT + does occur, the Processor block needs to sample CLR_ WAIT-and wait until the signal deasserts before attempting to access any devices that are reset by the Device Clear. The nature of the machine is such that DCl_INT
+
is asserted for only one state.The Device Clear machine is implemented using part of a 16R4 PAL {U l7}. The .t~ble below shows the
When PASSPORT is reset, it performs a mode initialization oper::ltion to determine how it should operate, once the reset has been removed. The INTR- line is used to set the operating mode. It is sampled by
very preliminary 7-26
Theory of Operation
PASSPORT one SCLK+ cycle prior -to the deassertion of RESET-. For proper operation this signal should be at a logical HIGH level at this time. Failure of this condition causes PASSPORT to initialize incorrectly and report to the Channel via the sense register that it is a CIO Level 1 card.