Read Amp Clipping Level Control Type 4179

Schematic Diagram

806-3848-100B

WRITE DATA STROBE GENERATION

The Write Data Strobe WDS is input from the inter-face at pin N and is supplied to an edge circuit edge. The Q output of the one-shot supplies a posi-tive 0.5 /lsec pulse which is gated through NAND gate IC7-3. provided that the transport is not in a test mode. The pulse then enables the write NAND gates ICll and IC15. gating the input write data to the write amplifier stages. It is also supplied as WDSI to Type 3849 Write Amplifier module. When ICl"';13 generates the write strobe. its Q output trig-gers the second ICI one-shot. which in turn inhibits IC6 for a 3.5 /lsec duration. inhibiting any pulses during that time.

If the transport is in test mode, TM true at pin K enables NAND gates IC5-2 and IC7-10. 12 while dis-abling NAND gate IC7-2. If Write Ready WRDY is true. crystal controlled data frequency fr' supplied from the Delay Timing module. is gated through NAND gate IC5-l2 and NOR gate IC5-6 to generate the test mode strobes. These are gated through the two IC7 NAND gates and direct-clear the write am-plifier flip-flops on this module and on the other Write Amplifier module. writing the all-l characters of the test mode.

WRITE AMPLIFIER STAGES

The data inputs are supplied from the data terminator card at pins R. S, T. and U, are inverted and then strobed through NAND gates ICll and IC15 by the write data strobe WDSI. generated at test point B.

The write channels are then supplied to the amplifier stages. each consisting of a divide-by-16 counter. a pair of flip-flops, and a pair of drivers. The am-plifier stages are digitally deskewable; where the delay of channels 0 through 7 is adjusted to coincide with that of the reference channel, channel p. when read back.

The delay of channel P is permanently set to the count of eight, equivalent to a quarter character delay. by counter IC8. Whenever the input data is 1. the WDS pulse is gated throughrCll-8 and direct-clears flip-flop IC9-13. The Q output of the flip-flop goes high.

removing the direct-clear from the rCB counter. The counter is then clocked by f1 at 32 times the data frequency until the count of eight. at which point the Qd output of the counter goes low and toggles rC9 flip-flop to the set state. The Q output of IC9 then goes low. locking the counter and toggling the output flip-flop IC9-9. During the next 1 character the same process is repeated with the output flip-flop IC9-9 toggling to the opposite state. When a 0 is input, the input NAND gate ICll-8 does not transmit the write data strobe, and consequently the write amplifier flip-flops are not toggled. The outputs of flip-flop IC9-5. 6 are then supplied to a pair of drivers rC10 which energize the write head, reversing the flux for each 1 while remaining unchanged for each O. as required for NRZl.

The operation of the amplifier stages of the eight other channels is identical to that of channel P, ex-cept that their delay is digitally adjustable. Four switches are connected to the parallel inputs of the skew delay counters of the eight channels, as shown for data channel O. The skew of each channel can be measured and adjusted during the write test mode.

which writes all l's characters, by observing the analog outputs at the Type 3631 Read Preamplifier module.

Trigger channell of a dual trace oscilloscope on the P channel so that one peak is easily observed. With channel 2 of the oscilloscope, observe the preampli-fier channel that is to be checked or adjusted. Set the switches on the write amplifier channel so that the peaks of the two observed channels coincide. A small amount of jitter will be seen on the channel being adjusted due to tape recorder dynamics. Re-peat the observations for all eight channels leaving the P chanriel as the reference.

Opening the switches reduces the count while closing them increases it. Thus when the switches are all opened the counter is direct-set to 16, gating the data character to the output without any delay. When the switches are all closed the skew counter is set at 0 and the character will be delayed 16 counts, or a quarter of a character time behind channel P.

WARS

The Write Amplifier Reset pulse WARS is input at pin P from the data terminator card, and is gated through NAND gate IC2-3, provided that Select 1 is true, to set flip-flop IC2-12. The 1 output of the flip-flop goes high, removing the direct-clear from shift register IC3. The register is then clocked by f1 at 32 times the data frequency. On the seventh

806-3848-200B

-pulse, the Qg: output of the register goes high and is inverted by "'lC~ to issue WARS!, resetting the write amplifier ttlp-flops on this module. W ARS1 is also output at pin H to Type 3849 Write Amplifier where it resets the flip-flops of the other amplifier stages. On the eighth pulse to the register the ~ out~ut goes high and is inverted by IC4-11, clearing flip-flop IC2 anq locking itself until the next WARS is issued by the interface.

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Write Amps,

Im Dokument KENNEDY Digital Tape Transport (Seite 134-137)