Problem Formulation

LetP denote the set of finite tuples of points in the plain P^def= R². A function f :P −→R^≥0 is calledconvexif for anyn ∈N,f restricted to{v ∈P | |v|= n} is a convex function of the vector of coordinates of the points in the tuple.

Let d be some prescribed distance function on the points in the plane and t,t⁰ ∈ Pⁿ. We say that t⁰ dominates t, if for each pair of indices i < j ≤n holds: d(t_i,t_j)≤d(t⁰_i,t⁰_j).

Definition 4.3.1 (Distance monotony) A functionf :P −→R^≥0 is called distance monotoneif and only if for all pair(t,t⁰)of tuples of the compatible size, if t⁰ dominates t, then f(t)≤f(t⁰).

Now we describe the input of the timing driven placement problem: We are given an acyclic timing graph. The nodes represent the outputs (sources) of the gates. Each arc represents an immediate data path (which is disjoint to all other gates) from one source of a gate to the source of another gate.

We are also given a set of gates C. Each nodev of graphG is assigned a gate γ(v) in order to allow multisource gates. This leads us to the notion of gate graph:

Definition 4.3.2 (Gate graph) A gate graph G = (V, E, C, γ) consists of directed graph (V, E), set of gates C and a surjective gate assignment γ : V −→C.³

To simplify our notion we have avoided standalone primary inputs/outputs which can easily be modelled by dummy gates.⁴

From now on, we will assume that we are given fixed convex, distance-monotone netlength and wiring delay estimation l, l⁰ : P −→ R^≥0. Note that each convex netlength estimations introduced in Section 4.2.3 is distance-monotone.

Some of the gates C⁰ ⊆ C are preplaced: we are given p ∈ P^C

0. The task is to extend this vector to p ∈ P^C minimizing the objective function (the sum of (quadratic) netlength). The complement C\C⁰ is denoted by C_m which is called the set of movable gates.

For the arcs in E, we are given intrinsic delays i ∈ P^E and positive gate and net resistances r^g,rⁿ : R^E≥0. Note that intrinsic delays are allowed to be negative which allows for modelling non-transparent arcs, those that are not propagated, but contribute to the objective function (sum of netlength).

3Note that in the case of single source gates,γis superflous and the gate graph is simply a graph on the set of gates as nodes.

4The careful reader may notice that we do not allow timing pins “inside” gates. At the first sight this may look like a restriction, but our approach and results can easily be extended to that situation, but “internal timing pins” induce superflous complication of formalism.

In fact, the current BonnTime implementation deals with gates containing internal pins without problems.

4.3. THE TIMING DRIVEN PLACEMENT PROBLEM 77 Furthermore, there is a vector of relative offsets o : P^E. In order to interpret the gate graph model, one has to understand thet there is a one-to-one cor-respondece between the arcs and the sink pins of the design. The offset of an arc is the difference of the offset of the tail node relative to its gate and the offset of the sink pin relative to the its gate (i.e. that of the head). More formally, for a given placement p, the geometric configuration of the pins of the net rooted at source u can be translated to the wiring configuration w:

w(u,p)^def= (p_γ(u),p_γ(e⁺

1)+o_e1, . . . ,p_γ(e⁺

k)+o_ek), where {e1, . . . , ek} is the set of arcs with tail u.

Delay d(e,p) over arc e with repect to placement p is defined as follows:

d(e,p)^def= ie+r^g_el(w(e⁻,p)) +rⁿ_el⁰(w(e⁻,p)).

Note that this delay function is convex in the placementpof the gates, since it is a nonegative linear combination of compisitons of convex and linear functions (p_g is linear inp).

Besides, we have prescribed arrival times on the boundary V⁰. These are the nodes which have either no entering or no leaving arc. Because of the structure of our constraints, this is equivalent to specifying lower limits on the arrival times at the sources of the graph and upper limits on the sinks. The set Vp

def= V \V⁰ is called the set of propagated⁵ nodes.

The careful reader may have noticed that the delay functions ignore the input pin capacitances. In fact, the contribution of the input pin capacitances to the delay can be computed in advance and added to the intrinsic delays. Therefore we omitted them to simpify our model.

To be found is a placement extending the preplacement, minimizing the (quadratic) netlength such that there exists a corresponding arrival time as-signment respecting the delay inequalities.

Now we summarize the definition of our problem:

5Note that we do not make a distinction between prescribed and required arrival times.

So nodes without leaving arcs with asserted required arrival times are not propagated by this terminology. This may seem piculiar at the first sight, but it is a consistent and usable point of view.

Placement with timing restrictions

Instance:

• A gate graph G= (V, E, C, γ). Let V⁰ denote the set of nodes without either entering or leaving nodes in G.

• Convex and distance monotone netlength and wire-delay and objective estimations l, l⁰, l⁰⁰ : P −→ R^≥0. We will further as-sume that l⁰⁰ is smooth and strictly convex.

• A subset C⁰ ⊆C and preplacement p⁰ ∈P^C

0.

• Pin offsets o∈P^E.

• Gate- and net-resistances r^g,rⁿ ∈R^E≥0.

• Intrinsic delays i∈R^E.

• Prescribed arrival times a⁰ ∈R^V

0.

Goal: Find a placement p : C −→ R² extending the preplacement p⁰ and corresponding arrival timesaextending the prescribed arrival times a⁰ minimizing the overall netlength

f(p)^def= X

v∈V

l⁰⁰(w(v,p)) subject to the timing constrains

a_e⁻+d(e,p)≤a_e⁺ for each arc e∈E.

Note that the objective function is convex and strictly convex in p and each constraint defines a convex area in the solution space P^Cm ×R^Vp. Therefore, each local minimum of the function is also a global minimum. Moreover, one can check that the placements of all optimum solutions are inside some offset adjusted bounding box (the bounding box extended by the maximum ocuring offset in each direction) of the preplaced gates. On the other hand, the delay inequalities imply that the arrival time vectora satisfies

au+X

e∈I

ie ≤av,

if I is an arbitrary (u, v) path andua source of the timing graph with prescribed arrival time. Similarly

a_v ≤a_u−X

e∈I

i_e

4.3. THE TIMING DRIVEN PLACEMENT PROBLEM 79 for an arbitrary v-u path I with sink u. This shows that all feasible solutions are located in an easy to compute compact box of the solution space.

The convexity of the problem motivates the usage of standard convex opti-mization methods introduced in Chapter 3