BPROI 16 16 16 16
-=
-=
BPRO/ 18 18 18 o 18
A 0 F G
P1 J2 J3 J4 J5
(OTHER (iSBC 80/10B) (OPEN) (OPEN)
MASTER)
Figure 2-6. Multibus™ Compatible Priority Resolution
BPRNI 15 15
BPROI 16 16
BPROI 18
G
P1 J2 J3 J4 J5
(OTHER (OPEN) (iSBC 80/10B) (OPEN)
MASTER)
Figure 2-7. Replacement Method Priority Resolution
2-24. MUL TIMODULE CONFIGURATION The iSBC 80/lOB board is Multimodule compatible.
Multimodule boards are special purpose, add-on circuit boards which reside directly on the component side of the iSBC 80/10B board and are interfaced through connector J 4. For specific Multimodule installation instructions, refer to the corresponding Multimodule hardware reference manual.
2-25. POWER FAIL AND MEMORY PROTECT CONFIGURATION
A power-fail and memory protect scheme may be implemented to preserve RAM conten~ in the event of an AC line failure. There are many ways to implement such a scheme, however Intel does not
2-18
recommend a specific method. A typical memory protect scheme could be implemented as follows:
NOTE
Detailed timing information for a typical power fail routine is provided in the Intel Multibus Specification, Order Number 9800683.
a. Connect +5 volt battery supply leads to P2-4 and P2-3 connectors. Connect returns to P2-1 and P2-2.
b. Remove or cut W 4 connection shown on figure 5-3, sheet 1, zone D6.
•
'7 I
ft
,
•
I•
I
•
•
..
•
•
•
•
c. Remove jumper 87 to 88 and install jumper 88 to 89. Refer to figure 5-3, sheet 2, zone D7. This connection enables PFINI to interrupt the CPU.
d. Connect MPROI to P2-20. Refer to figure 5-3, sheet 4, zone D7. MPROI must be generated by an external, battery operated latch, which is triggered by ACLO and PFIN/.
e. Connect PFSN I to P2-17 and PFSRI to P2-13.
Refer to figure 5-3, sheet 7. The PFSNI input and the PFSRI output should be connected to Port C on PPI circuit U16, using jumper posts 12 and 14, respectively. This enables the PPI to provide status to the CPU, to identify the power-fail interrupt as such, and subsequently reset the PFSRI signal upon restart.
NOTE
Ensure that the upper and lower portions of port C of the PPI circuit are configured to the appropriate mode to allow operation with PFSNI and PFSR/. Refer to Chapter il for PPI programming information_
2-26. USING RMX-80 SOFTWARE
If your iSBC 80/10B board is used with Intel RMX -80 software, some hardware modifications may be required for proper operation. Depending on the nature of your application and the types of extensions used, the iSBC 80110B board may require re-configuration of the following:
a. Baud rate selection jumpers.
b. Clock source jumper.
c. Interrupt jumper.
d. PCI control line jumpers.
e. Interface jumpers.
In addition, user software may require modification to initialize and format the Programmable Periph-eral Interface devices and the Programmable Communication Interface device.
Refer to the RMXIBO User's Guide, Manual Order Number 9800522, for complete instructions.
2-27. SERIAL 1/0 CABLING
Pin assignments and signal definitions for RS232C serial I/O interface are listed in table 2-16. An Intel iSBC 955 Cable Set is recommended for RS232C interfacing_ One cable assembly consists of a 25-conductor flat cable with a 26-pin PC connector at one end and an RS232C interface connector at the other end. The second cable assembly includes an RS232C connector at one end and has spade lugs at the other end; the spade lugs are used to interface to a teletypewriter. (See Appendix B for ASR-33 TTY interface instructions.)
Table 2-16. Pin Assignments for Connector J3 (Serial I/O Interface)
Pin Signal Name Pin Signal Name
1 CHASSIS GND 2
-3 TRANSMITTED DATA 4
-5 RECEIVED DATA 6 TTY RD CONTROL
7 REO TO SEND 8
-9 CLEAR TO SEND 10
-11 DATA SET READY 12
-13 GND 14 Tx ClK/DATA TERMINAL ROY
15 DATA CARRIER RETURN 16 TTY RD CONTROL RETURN
17 - 18
-19 -12 Volts 20
-21 - 22 RECEIVE ClKITTY Rx DATA
RETUFlN/+12
23 TTY Rx DATA 24 TTY Tx DATA RETURN
25 TTY Tx DATA 26 GND
Note:
Even numbered pins are on the component side of the board. Pin number 1 is on extreme right of solder side (as viewed from component side).
2-19
Preparation for Use
+12 and -12 Volt Outputs
A + 12 volt level may be applied to J3-22 if this pin is unused in your configuration (refer to figure 5-3, sheet 6), by installing jumper W3. Likewise, a -12 volt level will be applied to J3-19 if jumper WI is installed.
Ensure connector J3 is properly installed and the pins are connected to appropriate loads. Damage may result from improper connection.
For OEM applications where cables will be made for the iSBC BO/I0B board, it is important to note that the mating connector for J3 has 26 pins whereas the RS232C connector has 25 pins. Consequently, when connecting the 26-pin mating connector to 25-con-ductor flat cable, be sure that the cable makes contact with pins 1 and 2 of the mating connector and not with pin 26. Table 2-17 provides pin correspondence between connector J3 and the RS232C connector.
When attaching the cable to J3, be sure that the PC connector is oriented properly with respect to pin 1 on the edge connector. (Refer to the footnote in table 2-16.)
2-28. PARALLEL 1/0 CABLING
Parallel 110 ports E4, E5, E6, E8, E9, and EA are controlled by two Intel 8255A Programmable Peripheral Interface (PPI) devices and interfaced via edge connector Jl and J2. Pin assignments for Jl and J2 are listed in table 2-6; dccharacteristics ofthe parallel 110 signals are given in table 2-13. Table 2-10 lists some 50-pin edge connectors that can be used for interface to J1 and J2; flat crimp, solder, and wirewrap connector types are listed.
An Intel iSBC 956 Cable Set, consisting of two cable assemblies, is recommended for parallel 1/0 interfac-ing.
Both cable assemblies consist of a 50-conductor flat cable with a 50-pin PC connector at one end. When attaching the cable to Jl or J2, be sure that the connector is oriented properly with respect to pin 1 on the edge connector. (Refer to the footnote in table 2-16.)
The transmission path from the 110 source to the iSBC 80/10B board should be limited to 3 meters (10 feet) maximum.
The following bulk cable types (or equivalent) are recommended for interfacing with the parallel I/O ports:
a. Cable, flat, 5O-conductor, 3M 3306-50.
2-20
iSBC80/lOB
Table 2-17. J3/RS232C Connector Pin Correspondence
RECEIVE ClK/TTY Rx
DATA RETURN/+12V 22 24 grounded (refer to figure 5-3, sheet 8). As an optional connection, you may apply +5 volts to this pin by removing jumper pair 26-27 and installing 27-28.
Ensure connector J2 is properly installed and pin 1 is connected to an appropriate