The idea of using porous silicon and epitaxial thickening for the fabrication of thin silicon devices originates from the microelectronic industry [33-35] and has already been successfully transferred to photovoltaic (PV) applications [36, 37]. For this approach, a stack including a low porosity top layer (20-30% porosity) and a high porosity bottom layer (50-60% porosity) has to be electrochemically etched onto a silicon substrate. The etching process was described in detail in section 2.1. The properties that can negatively influence the epitaxial wafer quality are residual pores at the growth interface, high roughness values
and strain in the porous silicon crystal lattice. All these parameters would lead to a higher defect growth in the epitaxial silicon wafers and therefore to a worse electrical quality [8].
An example for such a porous silicon double layer is shown in Figure 2.5 left. During high temperatures above 800°C the porous silicon layers reorganize as described in subchapter 2.2. Because of the above described vacancy gradient the bigger pores in the high porosity layer will grow in size, while pores in the low porosity layer close to the interface will shrink or dissolve. At the surface of the porous silicon stack a pore-free layer will form, because the surface acts as a sink for vacancies which was first reported by Labunov et al.
[27]. This means that by adjusting the porous silicon layer stack, a high porosity detachment layer can be formed during reorganization together with a low porosity template layer for epitaxial growth (see Figure 2.5 right).
Figure 2.5 Double porous silicon layer stack for kerfless wafering before (left) and after reorganization (right), from [8].
Most research on enhancing the detached silicon wafer quality for solar cell application has been performed by the Interuniversity Microelectronics Centre (IMEC) and focused on adapting the porous silicon etching process. The aim was to minimize the surface roughness and strain in the porous silicon template after annealing by adjusting the porous silicon layer thicknesses and porosities [28, 38, 39].
In the case of two-layer porous silicon stacks, a trade-off between the layer roughness and strain has to be made [39]. For a thick low porosity layer (1300 nm) the root mean square (RMS) roughness increases for longer annealing times, whereas the out-of-plane strain is reduced. With a thinner low porosity layer stack (750 nm) the increase in roughness is reduced for longer annealing times, but the high porosity layer is not sufficiently supplied by vacancies from the thin low porosity layer to enable detachability after annealing.
Radhakrishnan et al. state that this trade-off between strain and roughness with layer thickness and annealing time can only be avoided using a new triple layer stack, which features two low porosity layers on top of one high porosity layer [40]. The first thin (approx.
100 nm) low porosity layer located at the growth interface is needed to achieve a good template with a planar surface and the second low porosity layer is needed to ensure that the high porosity layer is “supplied” with enough pore volume and therefore allows for easy detachment. The main disadvantage of this new layer stack is an increase in the required
etching time by approximately 25% - 40%. Unfortunately, no publications are available that show surface roughness and strain values for this new triple layer stack.
In this work it was not possible to develop and adjust an individual porous silicon stack, because no etching tool was available at Fraunhofer ISE. Therefore, a porous silicon layer stack developed at IMS (Institut für Mikroelektronik Stuttgart1) was purchased and only the reorganization process for this template was optimized. The layer stack is described in detail in chapter 4.1. The important difference to the triple layer stack proposed by Radhakrishnan et al. is that it consists only of one low porosity layer on top of two high porosity layers. The additional etching of the second high porosity layer increases the etching time only slightly.
It was the aim in this work to find out whether this purchased layer stack is suitable for good epitaxial growth of high quality epitaxial wafers after an optimized reorganization.
Besides a good template quality by means of roughness and strain, another important property of a suitable layer stack for kerfless wafering is the detachability of that layer.
Simulations have been performed by Radhakrishnan et al. to investigate the maximum stress in the first unbroken pillar at the detachment front of the high porosity layer [40]. The higher the stress, the more likely the pillar will break and this breakage will propagate to the next pillar until the wafer is detached from the parent substrate. The stress depends thereby on the pillar width and the pillar spacing which is illustrated in Figure 2.6. The pillars have to feature a minimum distance of 2 µm from each other and the pillar width should not exceed 150 nm. For this case Radhakrishnan et al. simulated stress values above 5000 MPa which seem necessary for easy detachment. It has to be kept in mind that those simulations have been performed for the case of identically shaped cylindrical pillars without considering any low porosity layer. Figure 2.6 can therefore only give a rough indication for the pillar spacing and width needed for easy detachment.
1 Institut für Mikroelektronik Stuttgart Allmandring 30a
70569 Stuttgart
Figure 2.6 Modelled values of the maximum stress in the first unbroken pillar for different pillar width and different pillar spacing. From [40]