6.6 Additional Constraints
6.6.1 Placement Density Constraints
In the VLSI placement step, the chip area is typically divided into so-calledregions,
Region,
density target and a density target is dictated for the chip. In each region, the ratio of the placement area of all non-fixed gates and the placement area of the region should not exceed this target. This ratio is called placement density (cf. Section 2.6) of the region. In the placement context, non-fixed gates comprise all gates that can change their placement position. In the context of gate sizing, non-fixed gates are those whose size we are allowed to change. A density violation occurs in a region
Density violation
if the current placement density exceeds the target.
We discussed in Section 2.6 that high placement density in a region in turn often implies a high pin density, which makes it more difficult for routing algorithms to connect the pins. The density target is an estimate of the density that can be realized in each region without impeding routing steps.
Gate sizing can induce local density violations because larger sizes consume more area. Similarly, gate sizing can create overlaps between gates, which have to be removed in a subsequent legalization step. A high placement density in a region complicates the work of the legalization algorithm. For example, Figure 6.3 shows the movement of gates during legalization after a global gate sizing that neglected density constraints. We conclude that it is beneficial to consider density in a gate sizing algorithm.
Previous works
Previous works on gate sizing usually take placement constraints implicitly into account by minimizing total gate area. Literature on simultaneous placement and gate sizing only considered small instances due to complexity and running time reasons. For example, Liu et al. [LSH08] consider delay-optimal placement and sizing of gate graphs with tree topology. This algorithm is heuristically extended to general acyclic graphs using Lagrange multipliers. Chen and Pedram [CHP00]
simultaneously size and place the gates on the k most critical paths in a design based on a geometric program formulation, and round the continuous solutions.
Cong et al. [CLL11] perform sizing and placement with respect to placement density in a Lagrangian relaxation framework. A constraint requires that the total gate area
6.6 Additional Constraints
Figure 6.3: The movement of gates during legalization after a global gate sizing.
Each colored line connects the placement location of a gate before le-galization with the location after lele-galization. The different colors cor-respond to the length of the movement from old to new location ranging from blue (shortest) to red (longest).
on the chip does not exceed a prescribed value. A parameterised quadratic term is added to the Lagrange function to punish such a violation. The corresponding parameter µ is refined by iteratively solving the dual problem with the projected subgradient method for different values ofµ. In the projected subgradient method, the Lagrange primal problem is solved in each iteration by iteratively minimizing the Lagrange function with respect to the placement variables and the size variables.
We show how placement density can be incorporated more directly:
Incorporating Placement Density Constraints
Suppose the chip area is partitioned into regionsR1, . . . , Rq,q ∈N. For each region
Rwwe are given a placement density targettargetwthat should be fulfilled. Usually, Rw, targetw
the density targets are equal for all regions, but may differ if certain regions are known in advance to cause difficulties for the routing tools. We obtain the following
constraints:
1
|Rw| X
gi∈Rw
area(gi)≤targetw, w = 1, . . . , q (6.9) where |Rw| denotes the free area of region Rw and gi ∈ Rw means that the area of gate gi is in region Rw. Note that we assigned each gate to exactly one region.
However, there does not necessarily exist a partition of the chip area into regions where the area of each gate lies in exactly one region. It is more likely that the area of some gates contributes to more than one region. In that case we assign the gate to the region that contains its center, or, if the center lies on the border of several regions, we assign the gate arbitrarily to one of these regions. We discuss how this assignment can be improved at the end of this section.
The area usage area(gi) of a gate gi depends linearly on its size (cf. Section 4.2) and exponentially on the size variable xi because of the variable transformation xi = log(ξi) (cf. Section 4.4.3). We writearea(xi) for the area of gate gi to clarify the dependency on the size variables. For x ∈ Xcont let r(x) ∈ Rq be the vector
r(x)
with entries
rw(x) := X
gi∈Rw
area(xi)−targetw· |Rw|.
Obviously, these are strictly convex functions of x ∈ Xcont. We introduce a La-grange multiplier µw for each region Rw, w = 1, . . . , q, and relax the constraints (6.9) in the Lagrange function (6.3):
L(λ, µ, x)
L(λ, µ, x) := cost(x) +X
e∈E
λe·delaye(x) +
q
X
w=1
µwrw(x), (6.10) with µ= (µ1, . . . , µw)t. The Lagrange dual problem is defined as
D(λ, µ), λ∈ F, µ≥0
sup D(λ, µ) := infx∈XcontL(λ, µ, x) (6.11) subject to λ∈ F, µ≥0.
Solving the Lagrange Primal and Dual Problem
It is easy to see that the Lagrange functions (6.10) and (6.3) are differ by a constant factor for each gate. Therefore Algorithm 5.1 solves the corresponding Lagrange primal problem for the continuous relaxation up to any desired accuracy.
Theorem 6.10 D(λ, µ)is differentiable for allλ, µ≥0with gradient (d(¯x), r(¯x))t, where x¯∈Xcont is the unique minimizer of L(λ, µ, x).
Proof. The proof of Theorem 6.3 can be extended naturally: The newly added constraintsr(x) are obviously strictly convex and continuous, therefore there exists a unique minimizer of L(λ, µ, x) for all λ, µ ≥ 0. The statement follows from Theorem 3.22.
6.6 Additional Constraints
Consequently, the projected gradient method finds a solution for the dual problem (6.11) if a strongly feasible solution exists.
Algorithm 5.4 or Algorithm 5.5 can be used to find a solution for the discretized Lagrange primal problem, but without any performance guarantees.
Improving the Assignment of Gates to Regions
In our current assignment each gate belongs to the region that contains its center, and we made the simplifying assumption that this assignment does not change in Algorithm 6.1. However, the placement area of a gate can contribute to more than one region. A partial assignment of gate area to regions would assign several region multipliers to the same gate, each of which relates only to the part of the gate area that lies in the corresponding region. Sizing the gate then requires computing the effects on several regions. We consider this adjustment to reduce the error introduced by allowing assignments to one region only not worth the effort.
Similarly, the location of the center can switch to another region after each sizing step. This is easy to check, and assigning a gate to a different region multiplier does not harm convergence of the projected gradient method for the continuous relaxation. It can be regarded as density decrease in the old region, and as density increase in the new region.