I REAL·TIME CLOCK REQUEST
THE PDP-15
Unlike its predecessors, the PDP-I5 was de-signed to provide a range of systems with both hardware and software. While early 18-bit ma-chines had evolved to include several con-figurations, the notion of a planned range for PD P-I5 systems was explicit from the start. As it turned out, the PDP-I5 evolved too, and over a considerably larger range than was antici-pated. Table 2 shows the range of systems that eventually developed; of these, only the models up through 15/40 were in the original plan.
As in the past, the goal for the new machine was to provide better performance/cost than the predecessor. The PDP-7 to PDP-9 transi-tion had provided a performance improvement, but not a big cost improvement. The new semi-conductor technology, transistor-transistor logic (TTL) available in dual inline packages, could provide the cost improvement required.
The 7400 and 74HOO series of TTL integrated circuits permitted clock speeds of 10 to 20 MHz and lower costs and higher packing densities than did the discrete circuits used in the PDP-9.
Not only did the higher packing densities lower the packaging costs, but they also permitted the
THE PDP-1 AND OTHER 18-BIT COMPUTERS 157 of the I8-bit series, while providing a number of options and additional features including an ad-ditional instruction set with an index and limit register for multiprogramming. The new TTL
technology had one substantial drawback, how-ever. Where the old discrete transistor tech-nology had used - 3 volt and ground signals, the new technology used
+
5 and ground. Thus, to permit the use of both existing peripheralsFigure 29. PDP-15/10.
and new peripherals, level converters on the I/O Bus were required.
In addition to the cost improvements antici-pated from the use of integrated circuits, it was also hoped that new memory systems available would offer both cost and performance im-provements. The PDP-I5 memory is contrasted with the PDP-I memory in Table 3.
With the new memories and changes in ad-dressing capabilities through the Index Register and relocation options, memory size could be expanded to 131 K words. A separate control unit, called the I/O Processor, handled the bookkeeping for the I/O channels and I/O Bus.
Figure 30 shows a typical PDP-I5 system. The two processors (main processor and I/O Pro-cessor) occupied only a third of the cabinet space of a comparable PDP-9 system, yet were faster and had more capability. While on the subject of cabinets, note that the packaging for the PDP-I5 reverted to the simplicity of the ear-lier PDP-I, PDP-4, and PDP-7 cabinets by us-ing a fixed mountus-ing structure rather than having the module connector blocks mounted on a door.
FANS FAN
LOGO
MEMORY
CP/IO
CP/IO
CONSOLE
TABLE
DOOR
DEC 19·INCH CABINET DEMENSIONS:
30 INCHES DEEP: 21·11/16 INCHES WIDE: AND 71·7/16 INCHES HIGH.
POWER SUPPLY
Figure 30. PDP-15 side/front logic layout.
The goals for the PDP-I5 were to obtain an 850 nanosecond cycle time, to be compatible with the PDP-9, to have a low manufacturing cost, to improve priority interrupt latency, to fit the basic system in one cabinet, to extend the length of the I/O Bus, and to improve main-tainability. The success in meeting these goals varied.
The goal of achieving an 850-nanosecond cycle time was exceeded, as the PDP-I5 was shipped with an 800-nanosecond cycle time. It was particularly gratifying that this goal was met and exceeded because there had been a number of obstacles to overcome. The central processor, memory, and I/O had been made asynchronous to reduce I/O latency, but this re-quired synchronizing logic that resulted in sig-nificant circuit delays. A dc (round-trip) interlocked memory bus had been designed so that speed independent memories could be used, but this caused communications delays.
Finally, to minimize cabling, a single set oflines had been used for communicating address and data information to the memory. This caused further communications delays.
THE PDP-1 AND OTHER 18-81T COMPUTERS 159
The PD P-9 instruction compatibility was achieved with three minor exceptions about which no complaints were received. Com-patibility for I/O devices was achieved by changing the receiver/driver modules to pro-vide the required conversions back and forth between the older peripherals and the new PDP-I5 I/O Bus.
To meet the manufacturing cost goals, a number of things were considered. The PDP-I5 was one of the first DEC computers to use in-tegrated circuits extensively. Because each logic type used in the machine would have to be spec-ified, purchased, delivered, and tested, it was important to minimize the number of logic types. (Note the similarity of this concern to that expressed in Chapter 4 with regard to min-imizing the number of flip-flop types in the TX-0.) The PDP-I5 was designed with 21 semi-conductor types, including integrated circuits, transistors, and diodes. All of them were avail-able from multiple suppliers. To simplify manu-facturing and field installation of options, the PDP-IS had fixed configuration rules. This was a mixed blessing because the fixed con-figuration rules resulted in higher costs from the greater number of partially filled cabinets. Mar-gin testing for the PDP-IS was planned using a combination of varying logic timing and tem-perature. Special test equipment was con-structed for the PDP-IS production line to
1/12 cabinet 1124 cabinet
5 planes
4 bits/plane 20 bits/plane
Planar stack Planar stack
18 mil 18 mil
3 3
permit rapid heat cycling of central processors and memories. In addition, a fast program loader system was designed using a PDP-8 with mUltiple DECtape units. This system permitted programs to be loaded into the memory of a unit being tested by merely pressing a button.
This saved considerable checkout time com-pared to the previous methods of loading diag-nostics via paper tape.
It was originally planned that manufacturing costs would also be reduced by using sub-assembly replacement. The concept was that if a processor, memory, power supply, or other enough material to allow the subassembly sub-stitution to take place.
. The manufacturing cost goals were not met during the production of the first 50 units, so an examination was made to determine which items were most costly. It was determined that most of the cost difficulty was in the mechanical packaging, and that the cabling, in particular, was costing more than anticipated. Sights were set on reducing the cabling complexity by using a single power harness that could be built and
tested on a jig. The cabling was reduced to one console cable, one teleprinter cable, one I/O bus cable assembly, and two memory bus ca-bles. In trying to limit console cabling, a time division multiplex communication scheme was designed to get the signals to the lights and from the switches. In this scheme, a number of sig-nals were transmitted on the same wires on a timeshared basis, and the console lamp fila-ments were used as storage elefila-ments. While this scheme was clever enough to gain the PDP-I5's only patent, it was generally unsatisfactory. It made the console logic so complex that when it failed, it was harder to fix than the processor.
The goal of reducing interrupt latency to two microseconds was not achieved. With the par-ity, memory protect, and memory relocation options implemented, and with adder and syn-chronizing delays added in, the latency could only be reduced to four microseconds; but that was acceptable.
The goal of packaging the basic system (cen-tral processor, I/O processor, console, and 32 Kwords) in one cabinet was met; it was a close fit, and there were virtually no spare module slots. Since few small systems were sold, it is not clear that this emphasis was warranted.
The goal of extended I/O bus length was achieved by switching from an unterminated, diode-clamped I/O bus such as the PDP-9 used, to a new, terminated I/O bus. A new set of bus transceiver modules was designed to provide greater speed and less bus loading. The new bus design, with cleaner signals and no reflections, combined with the new bus transceiver mod-ules, permitted the I/O bus to be extended to 75 feet. The penalty paid was higher power con-sumption and greater power supply cost than in the PDP-9.
The goal of better maintainability was par-tially achieved by equipping the logic with a means of monitoring 400 signal points. This feature was combined with a single step feature which permitted troubleshooting from the con-sole without the use of an oscilloscope. As it
turned out, the single step feature was used in-frequently because of the training required to use it properly.
Figure 31 shows the register transfer struc-ture of the PDP-I5 processor. It was based on elements and features used in earlier designs and had a basic data path which permitted the results from any of the 11 registers to be read into the arithmetic unit and then back into the registers. In order to achieve high speed oper-ation, a number of separate registers (such as the Step Counter, the Program Counter, and the Multiplier-Quotient registers), operated in
FROM I/O BUS
INPUT GATING ARITHMETIC UNIT
~TENDED - - - - ,
ARITHMETIC I
I
ELEMENTI
I I I I I I
Figure 31. PDP-15 processor register transfer diagram.
parallel with the basic data path. In this way, significant overlap occurred, permitting the 800-nanosecond cycle time. The contrast be-tween this design and the PO P-4 design is noteworthy. The PDP-4 had only four registers in the basic machine, but the use of integrated circuits in the PDP-15 permitted more registers to be used without so much concern for cost.
The first major extension of the PDP-I5 was the addition of the Floating-Point Processor (Figure 32) to enable it to perform well in the scientific/computation marketplace using FORTRAN and other algorithmic languages.
With the addition of the Floating-Point Proces-sor, the time for a programmed floating-point operation was reduced from 100-200 micro-seconds to 10-15 micromicro-seconds, giving nearly a
Figure 32. PDP-15 Floating-Point Processor register transfer diagram.
THE PDP-1 AND OTHER 18-BIT COMPUTERS 161
operations. For most machines, the difference between built-in and programmed data-types is higher; but, because the machine was originally designed to operate effectively without hard-wiring, the difference is quite low. Table 4 gives a summary of the performance improvements offered by the floating-point option.
The addition of the floating-point unit re-quired that a number of instructions be added to the machine. The irony of this extension is that the PDP-II and nearly all minicomputer instruction set extensions exactly follow this ev-olution.
A low cost multi-user protection system was added in the form of a relocation register and a boundary register. Because this was marketed as an add-on option, it degraded the machine performance more than necessary. However, the minimum machine cost maintained the per-formance/cost target.
The first PDP-I5 was shipped in February 1970, 18 months after the project had started. A number of difficulties had been encountered, in-cluding personnel turnover, that caused a two-month slip. However, the project at first cus-tomer ship was within the budget and, by 1977,
Table 4. Floating-Point Computation Times
Without With
790 machines had been shipped - more than the total of all other DEC I8-bit machines.
Two of the PDP-I5 models are of special in-terest. A dual central processor version and the PDP-I5/76. These are treated separately below.
DUAL CENTRAL PROCESSOR PDP-15