PCI Bus Errors

The PB always detects address parity errors when it is not the PCI master, even if it is not the selected target.

The PB detects data parity errors if it is either the master or the target of a transaction, and optionally reports them to the system. Address parity errors are reported using the SERR# signal. Data parity errors are reported using the PERR# Signal.

intel· 82454KXlGX (PB)

3.4.2.1 PB Master Operation on PCI

Master Abort. When the PB performs a master abort, if the command was not a Special Cycle, the event is logged by setting the Received Master Abort bit (bit 13) in the PCISTS Register. An interrupt can be generated on this event. Special Cycle commands, which are broadcast to all PCI targets, are always terminated with master abort. Therefore, master aborts during Special Cycle commands are not considered errors, and are never logged or reported.

Target Disconnect and Target Retry. Target disconnects and target retries are not errors, and are not logged or reported.

Target Abort. The PB logs a target abort by setting the Received Target Abort bit (bit 12) in the PCISTS Register. If the SERR# enable bit (bit 8) of the PCICMD Register is set, and the SERR# on Receiving Target Abort bit (bit 7) of the ERRCMD Register is set, this event is reported by asserting SERR#. When the PB asserts SERR#, the Signalled System Error bit (bit 14) in the PCISTS Register is set. Optionally, the PB reports a hard failure response to the host bus transaction (PB EXERRST Register). Note that this is not possible for posted writes because the response phase has already occurred.

Data Parity Errors. As a PCI bus master, the PB checks the data parity provided during read data cycles and monitors PERR# during write data cycles. The errors are logged by setting the appropriate status bits. If a parity error is detected, the Detected Parity Error bit (bit 15) in the PCISTS Register is set. To distinguish between read data parity errors and write data parity errors, the appropriate bit (bit 6 for writes, bit 5 for reads) is set in the ERRSTS Register. Errors are reported via the SERR# and PERR# signals. The conditions causing the assertion of SERR# due to data parity errors are summarized in Figure 5. The conditions causing the assertion of PERR# and the Detected Parity Error Status bit are summarized in Figure 3 and Figure 4. Note that for read data parity errors, the PB returns the corrupted data (with good parity/ECC) as the CPU read response data. For write data parity errors, the corrupted data has already been delivered to the target; it is not retried by the PB.

3.4.2.2 PB Target Operation on PCI

Target Disconnect. PB generated target disconnect is not considered an error and is not logged or reported.

Target Retry. Target retry is not an error and is not logged or reported. The PCI master is responsible for deter-mining the maximum number of retries.

Target Abort. When the PB issues a target abort it sets the Signaled Target Abort bit (bit 11) in the PCISTS Register. No further reporting or logging is done by the PB. The PCI initiator logs the target abort and may report the error.

Data Parity Errors. As a target on the PCI bus, the PB checks the data parity provided during write data cycles. If a parity error is detected during write data cycle, PERR# is asserted and bit 15 of the PCISTS Register is set. No further reporting or logging is done by the PB.

data parity error---;---...

parity error responses enabled 04h[6]

PERR#

70h[3]

PERR# on data parity error enabled

-82454KXlGX (PS) intel·

inbound data parity error

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Set for PCI Status bit 15 PERR# asserted on write data parity error _ _ _ (Detected Parity Error)

Figure 4. Logic Diagram of the Setting of the Detected Parity Error BitO

read data parity error SERR# 04h[8]

driver enabled parity error 04h[6]

responses enabled 70h[5]

SERR# on received parity error enabled write data parity error parity error responses enabled SERR# on transmitted

parity error enabled ERR#

Master Abort received Report Master Aborts Report Errors using SERR#

Target Abort received SERR# on received 70h

Target Abort Report Errors using SERR#

Address parity error parity error 04h[6]

responses enabled SERR# on address 70h[4]

parity error enabled Enable Watchdog lime-out Report Watchdog Time-out Report Errors using SERR#

Set/Observed AERR#

---i

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Set/Observed BERR#

---i

infel·

82454KXlGX (PB)

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82454KXlGX (PB) intel·

Figure 6. Dual Bridge System Configuration

intel· 82454KXlGX (PB)

Figure 8. BPRI# Arbitration Overlapped with Bridge Transfer

Dual PB Configuration (82454GX only)

82454KXlGX (PB) infel·

Table 10. Bridge Device Number Encoding

Im Dokument Intel4S0KX/GX PCIset (Seite 72-78)