1 .10 Ethernet Interface
3.9.14 Network Interface Transmit Descriptor Ring The network interface transmit descriptor ring (NITDR) contains a
transmit buffer descriptor for each transmit buffer (Figure ~5). It is located in a contiguous block of the network interface buffer RAM whose base address is formed by concatenating the contents of the NIIBW10 and NIIBW11 <7:0> (TDRA<23:0». Since the NITDR must start on an 8-byte boundary, bits <2:0> of this address must be zero. The size of the network interface transmit descriptor ring can vary between 8 and 1024 bytes depending on the number of 8-byte descriptors it contains. The number of descriptors must be a power of 2 between 1 and 128 and is determined by NIIBW11 <15:13> (NTBD).
1514131211109876543210
TRANSMIT BUFFER DESCRIPTOR 0
TRANSMIT BUFFER DESCRIPTOR 1
0 0 0
0 0 0
TRANSMIT BUFFER DESCRIPTOR n
: BASE
:BASE + 8
:BASE + 8n
:BASE + 8n
HA-XOO68-88
Figure 3-65 Network Interface Transmit Descriptor Ring
3.9.14.1 Transmit Buffer Descriptors
Transmit buffer descriptor n contains the base address, size, of a transmit buffer as well as status and error information. It is four words (eight bytes) in length and is located in the transmit descriptor ring at base+8n.
A representation of a typical transmit buffer descriptor (TBD) is shown in Figure 3-66.
TBDnWO TBDnW1 TBDnW2 TBDnW3
151413121110 9 8 7 6 5 4 3 2 1 0
TRANSMIT BUFFER DESCRIPTOR n
Figure 3-66 Transmit Buffer Descriptors Transmit Buffer Descriptor n Word 0
:BASE + 8n
MA-XOO69-88
Word 0 ofTBD n (TBDnWO) resides in the network interface buffer RAM at the base address of the NIIRDR +8n. This word contains a portion of the base address of the associated transmit buffer. The format for transmit buffer descriptor n word 0 is shown in Figure 3-67.
15141312111098 7 6 5 4 3 2 1 0
TBDnWO BADR < 15:0 > :8ASE + 8n HA-X0070-88
Figure 3-67 Transmit Buffer Descriptor n Word 0 Data Bit Definition
TBDnWO<15:0> (BADR) Buffer address. This field contains bits <15:0> of the 24-bit network interface buffer RAM address of the start of the buffer associated with this descriptor. Written by the host;
unchanged by the LANCE chip.
Architecture 3-1 05
Transmit Buffer Descriptor n Word 1
Word 1 of TBD n (TBDnWl) resides in the network interface buffer RAM at the base address of the NIIRDR +Bn+2. This word contains a portion of the base address of the associated transmit buffer as well as status and error information. The format for transmit buffer descriptor n word 1 is shown in Figure ~B.
151413121110 98 7 6 5 4 3 2 1 0 TBDnW1
OWN ERR RSV
MRE _ _ --' ORE _ _ _ --'
OEF _ _ _ ---' SW _ _ _ _ --' ENP _ _ _ _ _ --'
BADR < 23: 16 > : BASE + 8n + 2
HA-XDD71-88
Figure 3-68 Transmit Buffer Descriptor n Word 1 Data Bit Definition
TBDnWl (OWN) Owned flag. This bit indicates whether the descriptor is
<15> owned by the host (OWN
=
0) or by the LANCE chip (OWN=
1). The LANCE clears OWN after filling the buffer associated with the descriptor with an incoming packet. The host sets OWN after emptying the buffer. In each case, this must be the last bit changed by the current owner, since changing OWN passes ownership to the other party and the relinquishing party must not thereafter alter anything in the descriptor or its buffer.
TBDn WI (ERR) Error summary. This bit is the logical OR of the COE,
<14> CAE, UFE and RTE bits in this descriptor. Set by the LANCE chip and cleared by the host.
TBDnWl (RSV) Reserved. The LANCE chip will write a zero in this bit.
<13>
TBDnWl
<12>
(MRE) More retries. The LANCE chip sets this bit when more than one retry was required to transmit the packet. Cleared by the host.
Data Bit TBDnWl
<11>
TBDnWl
<10>
TBDnWl <9>
TBDnWl <8>
TBDnWl
<7:0>
Definition
(ORE) One retry. The LANCE chip sets this bit when exactly one retry was required to transmit the packet. Cleared by the host.
(DEF) Deferred. The LANCE chip sets this bit when it had to defer while trying to transmit the packet. This occurs when the network is busy when the LANCE is ready to transmit. Cleared by the host.
(STP) Start of packet. This bit is set by the host to indicate that this is the first buffer used for this packet. STP is not changed by the LANCE chip.
(ENP) End of packet. This bit is set by the host to indicate that this is the last buffer used for this packet. When both STP and ENP are set in a descriptor, its buffer contains an entire packet;
otherwise two or more buffers have been chained together to hold the packet. ENP is not changed by the LANCE chip.
(BADR <23:16» Buffer address <23:16>. This field contains bits <23:16> of the 24-bit network interface buffer RAM address of the start of the buffer associated with this descriptor. Written by the host; unchanged by the LANCE chip.
Transmit Buffer Descriptor n Word 2
Word 2 ofTBD n (TBDnW2) resides in the network interface buffer RAM at the base address of the NIITDR +8n+4. This word contains the size of the associated transmit buffer. The format for transmit buffer descriptor n word 2 is shown in Figure 3-69.
151413 12 11 10 9 B 7 6 5 4 3 2 1 0
TBDnW2
I, I, I, I, I
BSZ < 11 ,0 > ,BASE + aN + 4MA-X0072-88A
Figure 3-69 Transmit Buffer Descriptor n Word 2
Architecture 3-1 07
Data Bit Definition
TBDnW2<15:12> These bits must be set by the host to ones. Unchanged by the LANCE chip.
TBDnW2
<11:0>
(BSZ <11:0» Buffer size. This field contains the size (in bytes) of the associated transmit buffer in two's complement form.
Note that the minimum buffer size is 64 bytes (to allow enough time for chaining buffers) and the maximum buffer size is 1518 bytes (the largest legal Ethernet packet). Written by the host;
unchanged by the LANCE chip.
Transmit Buffer Descriptor n Word 3
Word 3 ofTBD n (TBDnW3) resides in the network interface buffer RAM at the base address of the NIITDR +8n+6. This word contains error information and a time domain refiectometer. The contents of this word are valid only when the ERR bit in TBDn W2 has been set by the LANCE chip.
The format for transmit buffer descriptor n word 3 is shown in Figure 3-70.
151413121110 9 8 7 6 5 4 3 2 1 0 TBDnW3
SUE
UFE
RSV
COE _ _ ---' CAE _ _ _ ....J
RlE _ _ _ ---'
TOR < 9:0 > :BASE + 8n + 6
HA-XOO73-88
Figure 3-70 Transmit Buffer Descriptor n Word 3
Data Bit
(BUE) Buffer error. This bit is set by the LANCE chip during transmission when it does not find the ENP bit set in the current descriptor and it does not own the next descriptor.
When BUE is set, the UFE bit (below) is also set because the LANCE chip continues to transmit until its silo becomes empty.
BUE is cleared by the host.
(UFE) Underflow error. This bit is set by the LANCE chip when it truncates a packet being transmitted because it has drained its silo before it was able to obtain additional data from a buffer in memory. UFE is cleared by the host.
(RSV) Reserved. The LANCE chip will write a zero in this bit.
(COE) Late collision error. This bit is set by the LANCE chip to indicate that a collision has occurred after the slot time of the network channel has elapsed. The LANCE chip does not retry after a late collision. COE is cleared by the host.
(CAE) Loss of carrier error. This bit is set by the LANCE chip when the carrier present input to the chip becomes false during a transmission initiated by the LANCE. The LANCE chip does not retry after such a failure. CAE is cleared by the host.
(RTE) Retries exhausted. This bit is set by the LANCE chip after 16 attempts to transmit a packet have failed due to repeated collisions on the network. (If the DRTY bit of network interface initialization block word 0 (mode word) is set, RTE will instead be set after only one failed transmission attempt.) RTE is clear~ by the host.
(TDR) Time domain refiectometer. These bits are the value of an internal counter which is set by the LANCE chip to count system clocks from the start of a transmission to the occurrence of a collision. This value is useful in determing the approximate distance to a cable fault; it is valid only when the RTE bit in this word is set.
Architecture 3-109