Length: Standard with simple external connections, shifting left.
o
When a logic LOW is applied to the MODE, CONTROL input, a shift right op-eration is performed by clocking at the CLOCK 1 input. In this mode, serial data is entered at the SERIAL INput. CLOCK 2 and parallel inputs A through
o
are inhibited.When a logic HIGH is applied to the MODE CONTROL input, it allows entry of parallel data through inputs A through D and CLOCK 2. This mode per-mits parallel loading of the register or, with external interconnection, shift left operation. In this mode, shift left can be accomplished by connecting the output of each flip-flop to the parallel input of the previous flip-flop; that is, D output to C input, etc., and serial data is entered at input D.
Two clock inputs are available which permit separate clock sources to be used for the .shift right and shift left modes. If both modes can be clocked from the same source, the clock input may be applied to both CLOCK 1 and CLOCK 2. The transfer of information to the output pins occurs when the clock input goes from a logic High ,to a logic low.
SPECIFICATIONS
Shift Freq= 10 MHz (max) Propagation Delay
From:
CLOCKS Set-up Ttn'!e:
To:
High or low Output = 40 ns (max) SERIAL Input A, B, C, D = 20 ns (min)
MODE CONTROL with respect to CLOCKS = 25 ns (min)
M239
THREE 4-81T COUNTER/REGISTER
Length: Standard Height: Single Width: Single
C~
CLEAR
CLOCI( 1
M~C~lJR~1~ __ ~ __ -F3~) ______ +-~-,~ __ ~ __ -.
(CLOCK 21
Volts
t~D
E3 {SAME AS E51
U (SAME AS E5)
Power mA 70.0
70
Pins
C2.T1 A2
FLIP-FLOPS
M SERIES
~.>.:..:!.j_ ... L2_110{QO
The M239 Module consists of three high-speed, 4-flip-flop stage elements suitable for use as a storage register or a counter. Each of the 12 flip-flops has a data line input, and data information is entered by a COUNT/LOAD signal associated with each 4-bit stage. The output of the flip-flops assumes the logic state of the data inputs when the COUNT/LOAD input signal is High.
When the COUNT/LOAD signal is Low, the data inputs are disabled, pro-vided the clock inputs are inactive.
The QA output of each latch within a 4-stage element is connected to the toggle (T) input of the following latch. This allows the module to be used as a high-speed counter or serial-to-BCD converter.
The counters will accept frequencies of 0-50 MHz at the CLOCK 1 input, and inputs and outputs are TTL or DTL compatible.
FUNCTION
When operated as a serial counter, the Qo output of a 4-latch element must be connected to the CLOCK 1 input of the following 4-latch element. The separate Cl'EAR inputs may also be externally connected to reset all latch outputs using ooe CLEAR input signal (High transition). Output QA maintains 10 unit load capability in addition to driving the CLOCK 2 input. Refer to the Function Tables for the output levels of each count. . SPECIFICATIONS the clock 1 input of next 4-latch element.
M2500
DUAL 64 WORD X 4 BIT FIRST-IN FIRST-OUT SERIAL MEMORY
Length: Standard memory elements can also be paralleled, using external logic, to form storage for 64 8-bit words.
72
FUNCTION
The first 4·bit word is entered into the memory register by initiating a High SHIFT IN pulse when the INPUT READY signal from the memory is High.
With no data word previously stored in the first location of memory, the INPUT READY signal will be High. As the word enters the first memory loca·
tion, the INPUT READY signal becomes Low and remains Low until the SHIFT IN pulse is brought Low. The Low transition of the SHIFT IN pulse transfers the first 4·bit word into the second memory location, and the INPUT READY signal again becomes High. The internal control logic then sequences the word to the first-out or 64th memory location which causes the OUTPUT READY signal to become High. This indicates that the first word entered is available to be read at the output. The second 4-bit word can then be entered into memory and is automatically stacked at th&output. To read a word from memory and shift the next word to the output, a High SHIFT OUT pulse is required and causes the previously High OUTPUT READY signal to become Low. The data is shifted out by the trailing edge of the SHIFT OUT pulse when the OUTPUT READY signal is Low. The next 4·bit word is then automati·
cally shifted to the 64th location causing the OUTPUT READY signal to again become High. When all locations are empty, OUTPUT READY will remain Low.
When all the memory locations are full, the INPUT READY signal is held Low until a word is read, resulting in a vacant location.
APPLICATIONS
The M2500 can be used as a synchronous or asynchronous serial storage device or as a buffer unit for data communication between devices operating at different data rates. The M2500 can be serial connected to increase the total number of 4·bit memory locations or connected in parallel to extend the word lengths. Both data and control inputs and outputs are direct TTL and DTL compatible.
FUNCTION
The following input/output diagrams indicate the timing relationships and logic levels required to write into or read data from memory.
INPUT TI'MING
INPUT I.SV READY
ov
SHIFT l.SV IN
ov
DATA IN lDo-DJ)
73
OUTPUT 1.5V~
READY OV
tlR+ (Input Ready HIGH Time) tlR- (Input Ready LOW Tirt:1e)
OUTPUT TIMING
tov+ (Control Overlap HIGH Time) tlSI (Data Input Stable Time) too (Data Input Delay Time) tOR+ (Output Ready HIGH Time) tOR- (Output Ready LOW Time) tDH- (Data Hold Time)
NOTES:
300 ns (typ.) 300 ns (typ.) 100 ns (min.) 400 ns (min.) 25 ns (min.) 300 ns (typ.) 450 ns (typ.) 75 ns (min.)
tlR+ is referenced to the positive going edge of IR or SI, whichever occurs later.
tlR- is referenced to the negative going edge of IR or SI, whichever otcurs later.
tlD is referenced to the positive going edge of IR or SI, whichever occurs later.
tOY+ is referenced to the positive going edge of IR or SI, whichever occurs later. Control signals include Input Ready, Shift In, Output Ready, and Shift Out.
Data must be stable for tSDI or tlll+, whichever is shorter.
Input data must remain stable duri'ng timing window tSDI. Both SI and IR must be HIGH for tOY+.
tOR+ is referenced to the positive going edge of OR or SO, whichever occurs later.
toR- is referenced to the negative going edge of OR or SO, whichever occurs later.
tOH is referenced to the negative going edge of OR or SO, whichever occurs later.
toV+ is referenced to the positive going edge of IR or Sf, whichever occurs later.
Both SO and OR must be HIGH for t OY+.
Inputs SHIFT IN
DO-D3
SHIFT OUT
MASTER RESET
Outputs
INPUT READY
OUTPUT READY
QO-Q3
A High on this input causes INPUT READY to go Low and data to the shifted into the memory. Data will be-gin to shift to the last empty location when this input is brought Low again. Minimum pulse width is 100 ns.
Data must be valid within 25 ns after SHIFT IN goes High. SH 1FT IN must only be brought High when IN-PUT READY is High. Minimum Low time for SHIFT IN is 100 ns.
Data inputs. Data must be valid within" 25 ns after SHIFT IN goes High and should remain valid for at least 400 ns.
A High on this input initiates the output shifting pro-cess. Data will remain valid until 70 ns after both SHIFT OUT and OUTPUT READY have gone Low. Mini-mum pulse width is 100 ns. SHIFT OUT must remain
Low for at least 100 ns. "
Clears all memory locations.
Indicates when data may be loaded into the memory.
Goes Low 300 ns (typ) after the leading edge of SHIFT IN and goes High again when the next data word may be loaded. INPUT READY remains Low when the memory is full.
Indicates when data is valid at the output of the memory. OUTPUT READY goes Low 300 ns (typ) after the leading edge of SHIFT OUT and goes High again when the next word has "been shifted to the output.
OUTPUT READY remains Low when the memory is empty.
Data outputs. Data is valid at the outputs whenever OUTPUT READY is High, even if SHIFT OUT is Low.
Data will change 75 ns after OUTPUT READY goes Low. Typical propagation time from input to output of an empty memory is 10 p.S.