Installation and Operation
68040MP PROCESSOR INTRODUCTION
1.1 This section provides an introduction to the 68040MP processor board, the 68040MP memory expansion, the software protection adapter (SPA), and the LAN/SCSI adapter. This information is organized into three major topics:
• Features
• Specifications
• Reference documents
The 68040MP processor (Figure 1-1) is an advanced general-purpose processor for use in single processor and multiprocessor computing systems based on the NuBus"'" high-speed data bus. The 68040MP processor provides significant per-formance improvements over both the original 68020-based System 1500 proces-sor and the 68030-based System 1500 procesproces-sor, and serves as the basis for high-performance models System 1500 Computer. Several application-specific integrated circuits (ASICs) provide superior functionality. Through the use of memory expansion boards and the use of ASICs, space requirements on the pro-cessor board have been reduced and additional functions have been added to the processor assembly. Located on the 68040MP processor assembly is a SCSI Bus controller and a high-performance LAN 802.3 Ethernet controller.
Dynamic random-access memory (DRAM) chips on the piggyback memory ex-pansion (Figure 1-2) provide local storage for processor data and instructions. Er-ror-checking and correcting (ECC) logic protects the expansion memories. Cache memory provides high-speed memory access for enhanced performance.
The SPA (Figure 1-3) provides a hardware identification number for correlation with a software password required by TI System V operating system software. The SPA provides terminal connections for a system maintenance terminal (SMT), and must be installed on the processor that serves as the system test boot master (STBM).
The on-board SCSI Bus controller, with the addition of the LAN/SCSI adapter, provides a high performance SCSI interface that maximizes data throughput and minimizes command processing overhead. The MC68010 microprocessor pro-vides bus control, status, and data transfer operations for a maximum of seven mass storage devices on the SCSI bus.
The high performance LAN controller provides a single-channel interface be-tween the host computer and a local area network (LAN). A switch located on the LAN/SCSI adapter assembly allows the LAN controller to be configured to sup-port either the IEEE 802.3 Ethernet (AUI) or the IEEE 802.3a Cheapernet (BNC) standard.
NuBus is a trademark of Texas Instruments Incorporated.
68040MP 1-1
68040MP Processor Introduction
The LAN/SCSI adapter, Figure 1-4, is a peripheral cable adapter board connect-ing to connector P3 on the backplane of the slot containconnect-ing the 68040MP proces-sor assembly. It provides for either an AUI or BNC LAN connection, as well as a SCSI bus controller to support external SCSI mass storage devices. Located on the lower left edge of the adapter is the switch used to select AUI or BNC.
Figure 1-1 68040MP Processor
COMMISCSI inter:race (COSI) ASIC 68010 microprocessor
SCSI ROM
I
22557941.30]1-2 68040MP
LED indicators
memory expansion connector
P3 LAN/SCSI P2 SPA
connector connector
I.AN controller bus interface interface (LCIF) ASIC (BIF) ASIC
connector
memory interrace (MIF) ASIC 68040 microprocessor
SBCto NuBus interface (SNIF) ASIC
real time clock (RTC)
Installation and Operation
68040MP Processor Introduction
Figure 1-2 68040MP Memory Expansion Board
connectors ~,
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CJCJCJCJ CJCJCJCJ CJCJCJCJ CJCJCJCJ CJCJCJCJ CJCJCJCJ CJCJCJCJ
CJCJCJCJ
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2557941-35I
Figure 1-3 Software Protection Adapter
11....&....11.._ 9600-baud port
1200-baud port
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2557941-8I
Installation and Operation 68040MP 1-3
68040MP Processor Introduction
Figure 1-4
Features
1-4 68040MP
LAN/SCSI Ada:pter
NuDus connector " "
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2557941-28I
N--.
SCSI bus (!onnectorAUllBNC selection switch DNC
AUf
1.2 The 68040MP processor assembly provides a number of features that en-hance system pe:rformance. Key features of the 68040MP processor include the following:
• The virtual memory system allows the microprocessor to access the full 4-gigabyte address space without regard to the much smaller amount of physi-cal memory available. The demand-paged memory management scheme moves fixed··size pages of data between memory and mass storage disk drives.
• The 68040 enhanced 32-bit microprocessor, operating at 33.3 megahertz, serves as the central processor, bus controller, and memory management 1llnit.
The 68040 includes instruction pipeline logic, data and instruction cache me-mories, and other enhancements for high-speed operation.
• 128-kilobyte cache memory provides high-speed access to often-used data and instructions.
• Memory expansion boards, using 4-megabit DRAM devices, provide 32- to 128-megabYltes of main memory. ECC logic protects against memory errors.
Installation and Operation
Specifications
Table 1-1
Installation and Operation
68040MP Processor Introduction
• Dual-bus architecture separates shared resources from processor~only resources, allowing overlap of microprocessor local bus cycles and NuBus in-put/output cycles.
• Nonvolatile random-access memory (NVRAM) with an internal battery pro-vides storage for system configuration parameters.
• Read-only memory (ROM) stores permanent board information and self-test programs.
• The interrupt controller internal to the Bus Interface ASIC (BIF) handles board interrupts and NuBus events.
• Timers provide time accounting, interval measurement, and a battery-main-tained real-time clock (RTC).
• The NuBus interface includes 16-word first-in, first-out (FIFO) buffers to maintain optimum data flow between the NuBus and the processor board.
• The on board LAN controller supports the IEEE 802.3 Ethernet (AUI) and the IEEE 802.3a Cheapemet (BNC) LAN standards.
• The on board SCSI bus controller supports the SCSI-2 interface standard and supports fast device reads up to 10 megabytes per second.
1.3 Thble 1-1 lists the hardware specifications of the 68040MP processor board.
68040MP Processor Specifications
Thiple-height Eurocard, with connectors and mounting provisions for piggyback 68040MP memory expansion 32 to 128 megabytes of ECC-protected DRAM using one to four memory expansion boards Parallel ECC logic detects and corrects all single-bit errors and detects a1l2-bit errors
132-kilobyte cache memory using 20-nanosecond static RAM devices with parity protection
8 megabytes accessible at the NuBus slot address, FsOOOOOO. All memory accessible via a loadable base register that biases the on-board and expansion memory into NuBus global address space
Supports NuBus slave reads or writes (8-bit bytes, 16-bit halfwords, or 32-bit words) from external master to memory or physical bus registers.
Accepts NuBus slave block transfers of 32-bit words.
68040MP 1-5
68040MP Processor Introduction
Table 1-1
Reference Documents
1-6 68040MP
68040MP Processor Specifications (Continued) Item
NuBus master operation
Specifications
Reads or writes external slaves in bytes, halfwords, or words. The SCSI controller performs NuBus block transfers as a master: however, the CPU performs only single transfers.
SCSI bus controller SCSI-2 Controller, SCSI reads of 10 megabytes per second +5 volts, 12.0 amperes
+ 12 volts, 0.04 amperes -12 volts, 0.02 amperes +5 volts, 1.2 amperes
10° to 35° C (50° to 95° F) -40° to 65° C (_40° to 149° F) 27° C (80° F) maximum 20% to 80% (noncondensing) 5% to 95% (noncondensing)
1.4 For additional technical information on the 68040MP processor and its ap-plication in different computing systems, refer to the following documents:
• IEEE Standard for a Simple 32-Bit Backplane Bus: NuBus, IEEE Standard 1196-1987, (Institute of Electrical and Electronics Engineers, Inc.)
• NuBus System Architecture General Description, TI part number 2537171-0001
• IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Standard 754-1985, (Institute of Electrical and Electronics Engineers, Inc.)
• TI System V Administrator's Guide, TI part number 2540539-0001
• NuBus Systems System 1500 Field Maintenance, TI part number 2549258-0001
Installation and Operation