The development of integrated circuits (ICs) is one of the main driving forces behind the performance of today’s systems in terms of computing power. The miniaturization leads to faster switching of these circuits and allows for a reduction of consumed electrical power. One of the difficulties that arises with the miniaturization is the proper electrical interconnection of system parts. For one, the power has to be supplied to all consuming devices of an electrical circuit. Also, the number of required interconnections increases with the number of interconnected systems parts. Certain signal paths can become relatively long and a scaling of interconnecting lines including a reduction of their cross-sections leads to increasing losses in the interconnect.
The packaging of integrated circuits has the following principal aims: Establishing a me-chanical and electrical connection between an integrated system and the remainder of the system, e.g., other components that are located on a printed circuit boards (PCB). The electrical connection is in general used for both exchange of information with the inte-grated circuit in form of electrical signals and provision of electrical power to the circuit.
Ensuring the quality of the signaling as well as the quality of the supplied electrical power is commonly referred to as signal integrity (SI) and power integrity (PI), respectively.
Two important established technologies that are used in the packaging of ICs are illustrated in Fig. 1.1. Figs. 1.1a and 1.1b depict the perspective and side view, respectively, of an illustration of the wire bond interconnect. The integrated circuit is placed on a package substrate or printed circuit board (shown in green) with the active chip area on the top, i.e. pointing away from the substrate. The electrical connection to the active chip area is established through metallic wires (e.g. made of gold, or aluminum [2, Ch. 19], [3]). These wires are known to introduce an inductance which reduces the interconnect performance of
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Active chip area
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Figure 1.1: Established and emerging technologies used in packaging of integrated circuits to establish the electrical and mechanical interconnection with other system parts: (a) per-spective view and (b) side view of an example for wire bonding. (c) perper-spective view and (d) side view of an example for flip-chip technology. (e) side view an example stackup of two stacked chips on an interposer.
1.1 Motivation and Context of this Work wire bonds at high frequencies [4, Ch. 4.5], [5,6]. An illustration of the flip-chip technology is depicted in Figs. 1.1c and 1.1d. The active chips are flipped towards the package substrate or printed circuit board and connected through metallic bumps. These bumps represent a much smaller inductance and therefore a smaller discontinuity in the signal path than the wire bonds. Another important advantage is that the complete chip area can potentially be used for the interconnection with the flip chip, while a connection is only possible from one of the four sides with wire-bonds.
The term 3D integration describes technologies which allow for the interconnection of com-ponents in integrated systems using all three spatial directions. Traditionally, integrated devices are fabricated in processes where the contacts are planar and the connection be-tween sub-components is also established horizontally with respect to devices, e.g., by the wire-bonding described before. This has several disadvantages including the limitation of the number of connections, long interconnection paths and potentially many discontinuities if many sub-circuits need to be connected.
The 3D approach mainly aims at decreasing the interconnect lengths and, at the same time, enabling larger numbers of connections between sub-circuits. One long-term goal in 3D integration is to use all three spatial dimension for the fabrication of active devices.
The connections between the devices is implemented along these dimensions during the process of device fabrication. An already more established way to fabricate cost-effective integrated systems consists in connecting the planar chips vertically by stacking chips and establishing electrical connections among them. When using dies manufactured with silicon technology the through connection called vertical interconnect access (via), which electrically connects the top and bottom side of a chip, is called through silicon via (TSV).
TSVs and their applications are illustrated in Figs. 1.1e and 1.2a.
The TSV establishes short interconnections compared to connected chips placed next to each other in the same plane. Also, the theoretical interconnect density is higher for con-nections through chips. When stacking multiple chips to obtain very compact systems, one major limitation, if compared to the placement side by side, is the cooling of active devices which becomes more challenging [7]. Fig. 1.2a gives an example for the environment in which TSVs are applied. They can be part of a silicon interposer to connect a package and several chips. The vertical interconnects in the silicon have a similar structures as those found in printed circuit boards. Differences in their electrical properties are briefly discussed in Sec. 2.5.
Apart from the also very challenging fabrication of such systems consisting of stacked chips, the interconnects have to be designed with care. The starting point of the investigations is the single via and its electrical properties in the typical interposer environment. This
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silicon dioxide layer with dSiO2=0.6µm
silicon layer with dSi=100µm
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Figure 1.2: (a) Example for the environment of a silicon interposer. (b) Microsection of a silicon interposer. (Photos embedded in both figures courtesy of Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin.)
1.2 Organization of this Work