6.1 INTRODUCTION
The basic problem encountered in interfacing MOS and bipolar integrated circuits involves the translation of voltage levels-generally, voltage levels of opposing polarities. Typical bipolar integrated circuits, such as the TTL type, use a 5 -V power supply. The typical p-channel enhancement-type MOS integrated circuit uses a negative-going power supply varying from -5 V to -30 V. MOS circuits are not standardized throughout the industry with respect to supply voltages. They operate with a variety of power-supply voltages and a wide range of logic swings. In this chapter we are concerned with translating logic levels between the bipolar and the MOS circuit for data transfer and clocking. We can use external discrete devices between the bipolar and MOS integrated circuits, but we prefer to interface directly for a cost savings. We will review those areas where direct interfacing has been possible, as well as those areas where additional discrete devices are required. Since TTL circuitry is the most common form in the bipolar world, we will be concerned primarily with interfacing between TTL and MOS.
The problems of interfacing from MOS to TTL are quite different than the TTL-to-MOS data transfer. The bipolar TTL totem pole output circuits have ample drive capability to provide the speed for driving most MOS capacitive loads, even under high fan-out conditions. Many MOS/LSI circuits are designed to operate with 5-V power supplies and thus are directly compatible with the power supply and data transfer. When the MOS power supply is larger than 5 V, a problem of voltage translation and logic swing occurs.
The MOS transistor, being a low transconductance, high impedance device, is not well suited for driving directly into a TTL load. The MOS transistor which will sink the 1.6 rnA from each standard TTL load must have a large transconductance.
In fact, the MOS transistors which drive external circuits from the chip are those of maximum transconductance. In cases where the logic swing for MOS is sig-nificantly larger than 5 V, the interface to TTL must contain discrete components or special bipolar interface integration.
The drive requirements are considerably reduced when MOS is used to drive low-power TTL loads. The low-power TTL gates supply a maximum of 0.18 rnA
179
to the MaS driver. The equivalent resistance of the MaS driver for the positive-logic zero level is 1,700 Ohms. These values compare with 1.6 rnA and 250 Ohms for driving standard TTL gates.
6.2 DIRECT COUPLING OF BIPOLAR TO MOS WITH Vss
=
VeeThe task of translating logic levels from bipolar to MaS circuits is much simpler if one of the power-supply potential levels can be shared. The most positive TTL supply level (5 V) is generally connected to the most positive MaS (substrate Vss) level. In fact, we can attempt to direct-couple both power supply levels as shown in Fig. 6.1a to discover the problems involved. Here the substrate potential Vss
Vee I Vss
--~-+-
-
--...-....::..:::....--TTL totem pole
~---~ r~
VGG Voo
MOS load (a)
Driver TTL MOS chip
(b) 4 . 5 . - - , - - - , - - - . - - - . 0
MOS off
~ :::e~~~~/s;:---+--.i---~~:·.~}VT ~
~ 2.0 -2.5 Vi
r 0
r ~
°6~t=======~~~~~~~~
0.4 2.4 4.5"4.5 TTLin (V)(c)
Fig. 6.1. Typical bipolar TTL circuits direct-coupled: (a) bi-polar TTL driving an MOS PELT inverter; (b) MOS chip showing external TTL circuits connected at input and output;
(c) interface transfer characteristics indicating noise-margin problem.
Load TTL
of the MOS chip is maintained at the positive bipolar power-supply level (Vee).
The MOS inverter must have a low threshold voltage for device Tl . A second circuit schematic illustrating a TTL driver and a TTL load both connected to an MOS chip is shown in Fig. 6.1b. The problem of voltage translation for these circuits is illustrated in Fig. 6.1c, which provides us with the TTL transfer characteristics.
Here the vertical scale has been calibrated on the left side for voltage levels refer-enced to system ground, and on the right to MOS substrate. Notice that the bipolar voltage of 4.5 V corresponds to a zero voltage level in the MOS circuit. The worst-case transfer characteristics for the TTL provide a positive logic low for voltages of zero to 0.4 V. Similarly, a positive logic 1 is obtained in the TTL circuitry for levels of 2.4 V and higher. As a result, worst-case design points on the transfer
In fact, the noise margin in this worst case is negative, and therefore unacceptable.
We conclude that we cannot drive the MOS circuit directly from the TTL where worst-case MOS thresholds are in excess of -2.1 V. A simple remedy is available for maintaining the voltage output from the TTL at a higher positive level. One can add a resistor RI between the TTL output and the positive power supply, as is shown in Fig. 6.2a. When this is done, the transfer characteristics of Fig. 6.2b can be obtained for a sufficiently small value of Rl . Notice that now the minimum voltage level from the TTL for a positive logic 1 is approximately 3.6 V, corre-sponding to a voltage on the MOS chip of -0.9 V. The higher voltage output obtained from the TTL gate or other bipolar driver circuit in this case, is now more acceptable and can provide noise margins that are quite adequate. If the unity gain point for thresholds of the MOS inverter ranges from -2.0 to -2.5 V, we have, in this case, a worst-case noise margin of 1.0 V, as shown in Fig. 6.2b. For the bipolar output voltage of a positive logic 0, we have no problem in maintaining good noise margin. For instance, one would expect the output voltage from the bipolar driver to increase toward 2 V before a false data transfer results in switching action in the MOS inverter. The two noise margins shown as derived from the the chip. A much better solution, illustrated in Fig. 6.2c, substitutes an MOS device for resistor RI . This device is designed with a resistance equivalent to the value desired.
182
-;
----._~--~--._--+_----~---~~---vss
TTL driver
(a)
(High W/L ratia)
+--+----Vo
Load MOS
4.5r-~---.---,0
3.5 i==+==:~~~A..---+
_____
L-l-l.0~
2 5
f--+---¥~9t---+---___.____i-2.0}
~
-2.5VT~
~ ~
NMS=1.6V
0.4
ot=t=======~~~~~~===:;:;~-4.1
Q4 45 -4.5TTL in (V) (b)
Vee----~----~--~----+_---~~--~~---VSS
TTL driver Load MOS
(c)
T, (High W/L
ratio)
+-+----Vo
::;:
Fig. 6.2. Pullup resistance improves the noise margin for data enter-ing the MOS chip: (a) diffused resistor pullup; (b) transfer charac-teristics; (c) improved circuit uses device for pullup.
vCCo---1I---+---_-_---_----~--Ovss
f ~:;:~~'"'.
rMOSloadS
~4--+-+-~-+----~j~~-OVGG
TTL driver Bootstrap Bootstrap Push-pull
Fig. 6.3. Increased drive capability near the MOS chip data input, with bootstrap pullup inverters switching a low-impedance push-pull stage.
6.3 INCREASED DRIVE CAPABILITY ON THE MOS CHIP
The input gates on an MOS/LSI chip may have a high fan-out to other MOS.
In cases where clocking is generated on the chip, or many logic gates fan out from a single input inverter, we must include a design for the interfacing inverter circuitry, which has a higher than average drive capability. Figure 6.3 provides an increased drive capability for capacitive loads branching out from this input inverter on the chip. This type of circuitry is required when the logic level or intermediate cascade gates will not permit one to drive these high capacitance loads directly from the bipolar external driving circuitry. In Fig. 6.3 a push-pull inverter consisting of transistors T7 and Ts is driven from two separate inverters, each having a bootstrap-pullup load. Driving the push-pull devices provides a maximum drive capability for capacitive loads on the MOS chip. This circuit has the advantage of low power dissipation but it does require dynamic clocking. An alternative circuit which also provides drive capability for highly capacitive loads is shown in Fig. 6.4a and uses a depletion-type load device. You will recognize this as the PDLT-type inverter.
Some charging transient time values for the PDLT-type inverter driving a relatively small O.5-pF load are shown in Fig. 6.4b. These values refer to the driver device with gate W/ L ratios of I, 2, and 4 and a constant f3 ratio of 20. The threshold voltage for the driver device is held constant at - 1.6 V, and the threshold VT for the depletion load is varied from +6 to +24 V. The charging transient time tI is the time lapse between the driver turning off and the output rising to 90 percent of its full value. The PDLT load provides a tI value as small as 9.7 ns in the case of the maximum VT and W/ L ratio. For loads of 10 pF, the values of tI increase by a factor of approximately 10.
In those cases where we have a higher threshold voltage on the MOS chip and require logic voltage swings in excess of that obtainable directly from the TTL or other integrated-circuit driver, we must go to either a discrete device or an open-ended collector driver. The bipolar driver shown in Fig. 6.5a provides the necessary
184 MOS/LSI Design and Application
Fig. 6.4. Increased drive capability with low-impedance PDLT inverter:
(a) circuit schematic; (b) rise-time tn vs. threshold (pinch-off) voltage of the load device with W /L ratio of the depletion device as a parameter and C1
=
0.5 pF.increased logic voltage swing required for higher-threshold MOS devices. In Fig.
6.5b the V88 voltage of 8.0 V is matched to the bipolar gate transfer curve. The load resistance TL provides the necessary pullup action and results in a logic swing of approximately 7 V. The resulting noise margins are 2.4 and 4.1 V. A similar large noise margin is obtained when one uses a substrate maintained at
+
14 Vand threshold values for the MOS circuit ranging from -3 to -5 V. Figure 6.5c illustrates the transfer characteristics obtained under these conditions. The 14-V power supply results in a logic swing from the bipolar driver of approximately 13.5 V. Corresponding noise margins refers to the MOS inverter of 2.9 and 8.6 V.
>
Fig. 6.5. Increased logic swing obtained for MOS from a TTL data source using proper selection of Vss and VGG: (a) circuit schematic; (b) noise-margin relationship for Vss = 8 V; (c) Vss = 14 V.
185
It is relatively easy to transfer data from a bipolar driver circuit into an MaS integrated circuit when the substrate of the MaS circuit is maintained at the most positive system voltage level. Figure 6.6a and b illustrates the relative ease of this data transfer. In Fig. 6.6a the single bipolar interface device operating with the pullup resistor provides an excellent noise margin for the MaS circuit. In Fig. 6.6b a Zener voltage translation diode is added to permit an increase in speed for the driving circuitry.
In those cases where the substrate of the MaS load is not maintained at the Vee positive power-supply potential, the interface circuitry becomes more difficult. In Fig. 6.7a a TTL driver is interfaced into an MaS load where the substrate of the MaS circuit is maintained at system ground. Here device Tl operates as a switched current source and provides current drive for T2• The necessary voltage translation
Bipolar driver
Vee
~--+----__ ooo Vss
(a)
MOS load
o-~~---~---~-~VSS
Driver
TTL active interface Discrete (b)
t--~----, I
}-I
LVDD
'---+--'---oVGG MOS
load
Fig. 6.6. Interface circuitry with increased logic swing for driving MOS circuitry from a bipolar driver. MOS sub-strate is at a voltage Vee level: (a) inverter with base-limiting resistor; (b) inverter with Zener voltage transla-tion.
TTL driver
r---~----~r---OOO
Active interface
(a)
+---i--0
Vee
DI MOS load
Bipolor data
(c)
Vee i
I 013k:
Driver TTL t
I I I
Discrete active interface
( b)
Fig. 6.7. Bipolar interface circuitry with increased logic swing for MOS load. MOS substrate is at system ground potential. (a) two-transistor translator; (b) single-transistor interface with diode pull-to-Vnn ; (c) complementary drivers with increased drive ca-pability.
t---+--oVo
MOS load
occurs through device TI , and transistor T4 is switched in and out of saturation conditions. The PNP device contained in the active interface circuit is generally not found on bipolar integrated-circuit structures such as the TTL type, and repre-sents an external discrete device. The PNP transistor Tl is again used for the circuit of Fig. 6.7 b for obtaining the desired voltage translation. Here, device Tl is operating