Figure 6.14: Chip layout. Blocks numeration: 1 – input buffer, 2 – bandgap refer-ence, 3 – CP and PFD, 4 – loop filter, 5 – VCO, 6 – CML divider, 7 – prescaler, 8 – sigma-delta modulator, 9 – programmable register, 10 – 11 GHz pad driver The reference frequency used for PLL measurements is 64 MHz. The bandwidth is chosen to be more than 1 MHz which results on one hand in phase noise degra-dation at frequency offsets from 5 MHz to 40 MHz due to the quantization noise of the third order sigma-delta modulator, but on the other hand clearly visible fractional spurs within the PLL bandwidth which are aimed to be compared for the case of dithered and undithered modulator.
Table 6.2: 11 GHz frequency synthesizer performance summary
Technology 0.13 µm CMOS
Supply voltage 1.5 V
Current consumption 63 mA
Occupied area 800×800 µm
Reference frequency 64 MHz
Output frequency range PLL capture range 10.24 - 12.55 GHz (18%) VCO tuning range 10.6 - 11.6 GHz (9.1%)
Frequency resolution 125 kHz
Phase noise In-band phase noise <–80 dBc/Hz Noise floor –140 dBc/Hz
Reference spurs –52 dBc
Fractional spurs –44 dBc
Maximum lock time 8 µs
The measured phase noise/spurious diagram of the generated signal for the case of undithered modulator is demonstrated in Fig. 6.15(a). The fractional control word is set to 0.3134765625 corresponding to the following binary representation:
Ak−1...0[n] = 01010000012. The least significant bit of the input word switched to ’1’ ensures the best-case spurious performance of undithered modulator. Syn-chronized with a reference frequency of fref = 64 MHz the spurious will appear at frequency offsets of n·(fref/(2·2k)) = n·31.25 kHz apart from the carrier which is confirmed by the measurements. The power of some fractional spurs in the obtained diagram exceeds –30 dBc level. Most of the spurs are well above –40 dBc.
After adding dithering signal to the subsequent accumulators, spurs move to the lower frequency offsets and their power decreases, yielding the spurious at frequency offsetsn·(fref/2k+m1+m2), wherek+m1+m2 = 14 is the number of bits in the third stage of the MASH modulator. The measured phase noise/spurious plot with dithered modulator is presented in Fig. 6.15(b). The fractional spurs are observed at frequency offsets of n·3.9 kHz and their power does not exceed –44 dBc level. Measurements confirm the simulation results.
Some of the observed spurious tones (at frequencies 38.8 kHz, 58.5 kHz and 200 kHz) common for both phase noise diagrams are caused by the external fac-tors: the second is generated by the reference crystal oscillator, and 200 kHz spur is probably introduced by the power supply cables, since 200 kHz is a common switching power supply frequency.
The overall synthesizer performance summary is presented in Table 6.2. The sigma-delta modulator changes the division ratio not with a unity step, but with a step of 2, which results in the frequency resolution of 125 kHz.
(a)
(b)
Figure 6.15: Measured phase noise/spurious diagram with (a) – disabled DC dithering in second and third stages, (b) – DC dither applied to the second and third stages
Conclusion
The current trend shows, that fully integrated sigma-delta frequency synthesizers realized in submicron CMOS technologies will soon become dominant in portable, low-cost wireless transceivers. In the current work mixed-signal interaction as-pects, which appear to be a bottleneck in integrated sigma-delta frequency syn-thesizer design, and optimized solutions for digital sigma-delta modulators are investigated. Several different implementations of digital sigma-delta modulators were described. The research focuses mainly on improvement of MASH 1-1-1 mod-ulator as one of the most efficient and widely used architectures at present time.
The described implementations offer reduction in area, advantageous switching noise distribution, and good tonal performance. The measurements of the fully integrated 11 GHz PLL fabricated in 0.13µm CMOS technology prove theoretical findings and simulation results.
The main achievements of the work are summarized below.
1. A dual edge triggered MASH modulator implemented in CMOS logic is pro-posed. The implementation distributes the switching noise power in such a manner that the first reference spur of a synthesizer is not degraded; instead, the glitch energy is shifted to the second multiple of reference frequency.
Modulator’s area is reduced by 15–20%. Possible application of the sigma-delta PLL controlled by the dual edge triggered modulator is a frequency synthesizer in an integrated transceivers working with ISM band standards with RF bandwidth below 200 MHz.
2. MASH 1-1-1 (three stages of first order each) sigma-delta modulator with DC dithering used for frequency synthesis applications is proposed [Solomko 06].
At the expense of minimum additional hardware such dithering topology allows to shift tones to the low frequencies and decrease their power.
3. An oscillator-based dither generator is proposed for the use in MASH 1-1-1 modulator. The generator consumes less current and area, produces much less supply switching noise than a conventional pseudo-random dither
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study of oscillator-based dither generator is presented.
4. MASH 1-1-1 modulator with direct feedback dithering is investigated. With a little penalty in tonal performance, such dithering topology requires no additional hardware to be implemented.
Possible applications for described modulators are low cost, fully integrated sigma-delta frequency synthesizers fabricated in submicron CMOS technologies.
Frequency Divider Implementation
A.1 Circuit Implementation of DX
1Block
DX1 is a part of the frequency divider shown in Fig. 5.25. It operates at frequency of 1.4 GHz. In Fig. A.1 the internal structure of DX1 is shown.
A heart of DX1 is a 5-bit resettable counter CR. Its circuit diagram is demon-strated in Fig. A.3. CR is a pipelined and optimized version of a synchronous ripple-carry counter presented in [Stan 98]. The propagation path is partitioned with a flip-flop placed between the third and fourth stages of a counter allowing the device to operate at frequency of 1.4 GHz. Simulated maximum critical prop-agation delay is 7 times shorter than the period of triggering signal (which equals 1/(1.4 GHz)). Such significant margin ensures the operability of the counter even with the presence of simulation inaccuracies and additional increase of propaga-tion delay caused by layout parasitics (which were not taken into account in the simulation). In order to provide bit-parallel output deskewing flip-flips are added after the first three stages of the counter.
In the circuit both static (DFFSET) and dynamic (DFFD) flip-flops are used.
When no reset function is required dynamic flip-flops are preferable because of a smaller occupied area and 4 times lower average and peak supply current than in static DFFs. Transistor implementation of DFFD is shown in Fig. A.7.
All blocks of DX1 are clocked by the input signal Fin. Counter CR generates digital ramp signal appearing at the bus b<0:4>. At each triggering step it is compared with the control word (int) which defines the division ratio. When the value accumulated by the counter reaches half of the desired division ratio COMP1
resets the RS-flip-flop RSFF and it generates the falling edge of the output signal Fout. When the value at b<0:4> becomes equal to the desired division ratio, COMP2 sets the output of RSFF to ’1’ (generating the rising edge at the port Fout) and resets the counter.
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it required two dummy clock cycles before outputting the ramp signal. Moreover, one cycle of Fin is skipped during the reset of the counter and another one unity delay is caused by the D-flip-flop at the output of COMP2 (see circuit diagram).
In order to make the division ratio equal to the control signal int, the value of 4 is subtracted from the int before applying it to the comparators COMP1 and COMP2. Block AD5 performs the subtraction. For this reason the values 1, 2, 3, and 4 for the control signal int are prohibited and they must fall in the range int∈[5; 31].
The other blocks of DX1 are responsible for generating triggering pulses for phase selector. As a source of pulses Fin signal is used. f rac value defines the number of pulses. At each triggering step block COMPT compares the output value of the counterb with the desired value f racand enables the gated clock cell CLKG latched by Fin until f rac≤b. During this time CLKG outputs the signal applied to its clock input. When the counter value exceeds the control wordf racCOMPT generates disabling signal for gated clock cell and no more pulses appear at the outputpulseuntil the next rising edge of divided signal Fout. Four dynamic flip-flops connected in series are aimed at compensating the 4-cycle delay introduced by the comparator COMP2 and the counter.
Since pulse count is defined between two rising edges of the divided signal for guaranteeing correct instantaneous division ratio phase-frequency detector must be rising-edge triggered.
The value f rac falls in the range: f rac ∈ [1;int−4]. The value of f rac = 0 is prohibited, since in such case the maximum number of pulses will be generated.
Fig. A.2 illustrates timing diagram of DX1 block for control words int= 10,f rac
= 3.