Microprogram Function

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Appendix 4 Microprogram Function

General

This appendix will explain the function of the CCC by presenting some parts of the microprogram. To understand this information, the reader must be familiar with the channel signals and the signalling (data and commands) between the computer and the different devices. For information about registers and commands, see Appendices 2 and 3. As a detailed example of the microprogram design, the read sequence is chosen (a device sends data to the computer). The reader can then follow other sequences by means of the microprogram list.

The microprogram of the CCC has a general design, which means that all types of channels can be handled (selector-, burst multiplexer-, and byte multiplexer channels). To interface the high-speed channel as fast as possible, some functions must be executed in hardware. These special functions are described in the detailed hardware description.

Start-up routines

The start-up routines (see Fig. 47) include internal tests, communication test and initiation routines of the CCC. These routines are entered at Power on (when power to the CPL is switched on), Reset (the Reset pushbutton on the front panel is depressed) or System reset (ordered from the channel at any time).

Power on/Reset

Immediately after power to the CPL is switched on or the Reset push-button is depressed, the lamps L1-L4 on the front panel are switched on.

Lamp 1 is then switched off as a sign that the program has started.

Then the program performs a test of the microprocessor. If the test is carried out correctly lamp 2 is switched off, else the program enters an error loop (see later on).

Then the program tests the line buffer, by writing and reading data (zero and one). If no errors occur lamp 3 will be switched off.

These two tests will take place very rapidly. That is to say, lamp 1-3 will only be on for a short while at power on or reset if no errors occur in the tests.

If an error occurs, only lamp 1 or lamp 1 and lamp 2 will be switched off depending on which test failed, and the program will stop. At program stop an error code will be available at the Y -bus.

E90002332E

70 Appendix 4

Power on or Reset Test

condition register

Microprocessor

test. Lamp 2 off r - - - ,

Line buffer test Lamp 3 off

Communication test Lamp 4 off

cee

initiation

Fig. 47. Start-up routines

System reset

Microprocessor test. Lamp 2 off

eee

initiation

System reset to eps

Lamp 3 and 4 off

End 2

ERICSSON

:s

Lamp 4 will be on until a communication test has been correctly carried out between the

eee

^{and the}^ePB.This test can not be entered until the system program has been loaded into the ePB, which means that lamp 4 might'be on for approximately 15 seconds before it will be switched off. If an error occur's lamp 4 will be steadily on and the program will enter the error loop.

If all tests have been carried out correctly (lamp 1 - 4 switched off) the program enters the

ece

initiation program. This means that the channel address to the ePL is set up in the

cce

address decoder. The channel address is built up by one high address (highest device address) and one low address (lowest device address). Between these two addresses, the

cec

detects a valid address to the CPL.

The two addresses are determined by the system program and are available in the communication memory, where the

cec

fetches the addresses and stores them in two registers (high address register and low address

Moreover, the registers in the microprocessor are reset in the CCC initiation state. The program then enters the disabled state.

NOTE

If there has been a Power on or a Reset start, the CPL is not yet connected to the channel. (The S~lect out signal of the channel passes the CPL unit both with high and low priority). The Select out signal can only be caught in the enabled state (the Enable lamp on the front panel on).

System reset

A System reset can be ordered at any time from the channel, when the CPL is in the enabled state (the Enable lamp on the front panel is on). The program then enters the same point as at Power on and Reset (address 0000(16) in the microprogram). By sensing a condition register (Enable, Disable and System reset) the program decides if it was a System reset.

The difference between Power on/Reset and System reset is, that the CCC is connected to the channel in System reset. The CCC thereby has to serve the channel ~uring the tests.

The System reset starts with a microprocessor test, as in the Power onl Reset state. If the test is carried out correctly lamp 2 is switched off. If the test fails, error codes are set up in the communication memory to inform the CPB, and the program enters an error loop still serving the channel.

If the microprocessor test was carried out correctly the program initiates the CCC (CPL addresses to the address decoder and reset of the micro-processor registers, see Power on/Reset) .

The program then sets System reset to the CPB (Syre to CPB command in the communication memory) and sends an interrupt to the CPB. While the CPB executes the System reset command, the CCC is serving the channel.

If the channel addresses the CPL in this state, the CCC immediately sends back CD busy status to the channel.

When the CPB has executed the System reset command, the CPB returns an interrupt to the CCC. The CCC acknowledges this interrupt by switching lamp 3 and 4 off.

This means that a' System reset can be noticed by watching the lamps on the front panel. A system reset rapidly switches lamp 1 and 2 on and off and makes lamps 3 and 4 glow steadily for about 10 seconds.

Since System reset occurs in the enabled state, the System reset program module ends by entering a general subroutine End 2, which resets different registers in the communication memory and in the microprocessor. For information about End 2 see later on.

The program then returns to the enabled'state.

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72 Appendix 4 ERICSSON ~

Disable

In the disabled state (see Fig. 48) the CCC is not connected to the channel, that is to say the Select out signal from the channel is by-passed via the relays on the CIB board both in high and low priority. The microprogram runs in a loop and can be affected only by the switches on the front panel or by interrupt requests from the CPB (which today is considered as an error). The Enable lamp on the front panel is off.

If Test is selected on the front panel the CCC enters a background test loop and can be ordered by the CPB to perform microprocessor -, R WM -, and communication tests.

If the Disable/Enable switch on the front panel is set to position enable, the program enters the module Dis ~ enable, which is a program for changing state to enabled.

~

Disabled

Test IRQ CPS Enabled

~ ! ¹

Test

back-ground loop Set un- Dis~enable

~

^expected^order

~

Tests orderd Interrupt CPS.

by CPS

(

Send enable

Error state.

!

Wait for go

~

Line buffer to CCC Connect

~

channel.

Affect relays and enable lamp

(

^Enabled

!

(

Dis~ enable

Enable

This program module, used for change over from disabled to enabled state, first sets up the status meaning enabled and then sends an interrupt to the CPB. When the CPB has performed the interrupt routine and returns to the CCC with a "go" commancl, the CCC ~hCl:Ilges over th~

line buffer to direction CCC.

Then the microprogram affects the relays in such a way that the Select out signal from the channel is fed in to the detector circuits of the CCC.

The output signal, which affect the relays simultaneously lights the Enable lamp on the front panel, and the program enters the background loop of the enabled state.

NOTE

Selection of high or low priority is made by means of the switch on the CIB board (Up - high priority, Down -low priority). See circuit description.

When the microprogram enters the background loop of the enabled state (see Fig. 49), the CCC is connected to the channel and the Enable lamp on front panel is on~ In the enabled state background loop the signals D IS (Disable from the switch on the front panel) and SEL (valid address and Select out from the channel) are tested. (IRQ CPB is actually also tested but not supposed to occure in current programs.) If none of the signals is present, the program checks the status word of one device. (from the Device status table in the communication memory). If there was no AT (Attention) or DE (Device end) in the status, the device address scanner (Scan) in the processor will be incremented and the program returns to the start of the background loop. The looping continues until an AT/DE status is found somewhere in the device status table, SEL is detected from the channel, or the EnablelDisable switch is set to position disable.

If a SEL is detected, it means that the channel wants to enter a write or read sequence, and the program enters the module Channel sel described later on.

NOTE

If the NormallTest switch is set to position test, the program immediately disconnects the CPL unit from the channel and stops the microprogram execution. This function is used as an emergency stop.

Enable~ dis

If a DIS is detected in the background loop of the enabled state, the Enable ~ dis microprogram module is entered. This program releases the relays in a special sequence (necessary for the fast channel), and sends an interrupt to the CPB telling that the CCC enters the disabled state.

When the CPB returns from the interrupt with a "go" command, the CCC switches over the line buffer to the CPB and enters the disabled state.

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Enabled background loop (SGR)

( Enable--.dis

When the status Attention or Device end is found in the device status table, the microprogram immediately enters the AT/DE module, (see Fig. 50). The program then transfers the status to the Stareg in the micro-processor and resets the Attention bit in the status register of the device status table. Then the Unit check bit (UC) in the device status is checked.

If the Unit check bit is set, there has been some error in the device. If so the status of the device is transferred to Senreg in the microprocessor

(

from Enabled

+

AT/DE

)

t

Store device status in Stareg

+

Calculate device address

9

Set Intbusy and Stareq in microprocessor

,

Raise Reqi to the channel

,

85 Wait for SEL

•

to Channel sel

Fig. 50. AT/DE

Then the "real" device address is calculated, since the address pointer in the Scan register in the microprocessor scans only between 00(16) and

IF(16) in the device table. That is to say, the Scan register address is added to the low CPL address, which is available in the CPLadrl register in the CPB communication section of the communication memory. The device address is then stored in the device address register (Adrreg) in the microprocessor.

To indicate that the CCC is now busy and cannot serve a call from the channel, the Status request and Interface busy bits in the Pgmsta register of the microprocessor are set.

Now all required information about the device has been set up in the microprocessor (device address, device status and, if Unit check was set, device sense).

The program status register (Pgmsta) in the microprocessor indicates that the CCC is busy (Intbusy bit set). The CCC can now set Reqis to the channel.

The tag in signalling to the channel proceeds via the Ticopy register in the microprocessor. Reqis in the Ticopy register is set and Ticopy is clocked to the tag in register, where Req in to the channel is raised.

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76 Appendix 4 ERICSSON ~

The program then enters a background loop (B5) waiting for a call back from the channel, that is to say the internally generated SEL signal. The SEL signal is generated when Select in is raised by the channel and the Bus in contains a valid address for the CPL unit. The SEL signal is fed to the test condition selector, where it is tested by the background loop.

Since the program is now waiting for a call from the channel, the module Channel sel (see Fig. 51) is entered when the SEL signal becomes active.

In the general Channel sel module, which is decribed in detail later on, there is a test if the call is an answer to the request. If so (if the Adr out is not raised in connection with Select out signal) the program immediately enters the module Srvstareq (Serve status request).

from B5

Device adr to Bus in.

Raise Adr in and Opl in Drop Req in

Tagdecode B

Reset Zero

Drop Ai:lfln

Tagdecode A

I

Set Zero

,11

Cmd out

t

+

Cmd

Reset Zero

I

Set Selres or Indisc

Ii,

Reset zero

Set Selres or Indisc

"

Return to AT/DE

(

Srvstareq

Sta

The Srvstareq program immediately answers the call from the channel by latching the device address (stored in Stareg of the microprocessor) to the Bus in, raising Opl in and dropping Adr in. Moreover Req in is dropped. The tag in operation is done via the tag in copy register, Ticopy, in the microprocessor, which always contains a copy of the present status of Tag in.

By that sequence the CCC has answered the channel call and enters the Tagdecode B table waiting for Cmd out to raise.

Tagdecode is a 16 byte table in the microprogram. When the module Tagdecode is entered the four lowest address bits to the microinstruction memory are taken from the tag out register (Adr out, Opl out, Cmd out and Srv out). The Tagdecode procedure is described in detail in under Channel interface logic.

In the Tagdecode B table three things can happen: Cmd out goes up (Zero is set), the channel orders selective reset (Selres) for the device (Selres in Pgmsta is set and Zero is reset) or the channel orders interface disconnect (In disc in Pgmsta is set and Zero is reset).

If Selres or Indisc was ordered from the channel in the Tagdecode B table the program immediately returns to the AT /D E program module. If Cmd out was raised, the program resets Adr in, resets Zero and goes to Tagdecode A.

In Tagdecode A the program is waiting for Cmd out to drop. When that happens, Zero is set and the program returns to the AT/DE program module. In Tagdecode A the program can order Selres or Indisc as in the Tagdecode B case.

When the program then returns to the AT/DE program module the can from the channel has been answered by transmission of the device address.

The channel can either have responded by saying "continue" or by ordering a Selective reset or an Interface disconnect.

What happened in the Tagdecode table is found out by testing Zero. If Zero is reset the program enters a module for serving Selective reset or Interface disconnect (ID/SR, described later on). If Zero is set the program enters the geperal module Sta for sending status about the device.

In the Sta subroutine (see Fig. 52) the device status, stored in the Stareg in the microprocessor, is clocked to the bus in register. Then Tag in is raised via the Ticopy register in the microprocessor and the program enters Tagdecode B waiting for Srv out or Cmd out to rise. When this happens there is a Zero test just as in Srvstareq. If Zero is reset, the Selres bit in Pgmsta is set and the program returns to AT/DE.

If Zero is set there is a test of Srv out. If Srv out is raised by the channel it means that the channel cannot receive the status just now. If so, sub-routine Stacksta is entered, to stack the status until the channel is ready to receive it. Stacksta subroutine is described later on.

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Fig. 52. Sta

Stack

Stacksta

to ID/SR

Appendix 4

Device status to Bus in.

Raise Sta in

Tagdecode B

Set CHAIN if chaining

Tagdecode A

Srvout Cmd out

No Zero

Srv out Cmdout

ERICSSON ~

from Srvstareq

t

Yes

to End 1 to ID/SR

If Srv out is not up a chaining flip-flop in the control circuits of the channel is sensed via the test condition selector. If the channel orders chaining (the flip-flop is set), the Chain bit in Pgmsta of the microprocessor is set. Then Zero is set and the program enters Tagdecode A waiting for Srv out to drop.

When Srv out drops the program returns to AT IDE and tests Zero. If Zero is reset, a selective reset has been ordered from the channel and the program enters the ID/SR module, for serving the reset. If Zero is set the program continues to End 1, which is a general routine for entering the

(

End 1

That means that we now have ended the sequence AT/DE, where an address and a status for a device have been sent to the computer. To return to the background loop of the enabled state, the program however must pass some general End routines.

The general End 1 routine (see Fig. 53) starts with a test of the Eos bit in Pgmsta (End of selection bit in the Program status register in the micro-processor). If DE (Device end) was sent to the channel the program continues in the End 1 module otherwise the End 2 module is entered.

End 1 continues by resetting the Stareg of the microprocessor. Then the program ~hecks Cubusy and Chaining (not described) and enters the Endsel program module.

from AT/DE

Reset Stareg

,.,--- ---I

I

Test Cubusy and Chaining :

I I

L___ _ __ --1

Device adr to Todev Reset Eos

Set interrupt to CPS

to End 2

Fig. 53. End 1 and Endsel

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80 Endsel

End 2

Appendix 4 ERICSSON ~

Endsel performs an acknowledge to the CPB that the status for a device is sent to the channel. First the device address is stored in Todev and Eos command is stored in the CCCcmd of the CCC communication memory area.

Then the Eos bit in Pgmsta is reset and an interrupt is sent to the CPB. The program then enters the End 2 module without waiting for an acknowledge of the interrupt sent.

The End 2 program module (see Fig. 54) first checks if the Cubusy bit in Pgmsta is set. If not, the Stareq and Intbusy bits in Pgmsta are reset and the line buffer is set in direction CCC. Then the Stareg (Status register) in the microprocessor is reset and the program returns to the background loop of the enabled state.

If we continue in our example, the device now has sent status Attention for a read sequence and the CPB is ready to accept a Read command from the channel. The CCC, however, has no information stored about a coming read sequence (CCC loops in the enabled state).

from Endsel or End 1

r - - - - - - - ,

I I

I Test I

I Cubusy I

I I

L___ _ _ _ ---1

Reset Stareq and Intbusy

Line buffer to CCC

Reset Stareg

to Enabled

(

Channel sel

Then, when a valid address and the Select in signal comes up, the program enters the Channel sel program module (see Fig. 55). This module was also used when the device sent status to the channel (AT/DE). This time the same t~sts are performed in the mo(:lule. from Enabled

Im Dokument Technical Description (Seite 184-200)

Appendix 4